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vc/amd/fsp/phoenix/FspmUpd: drop eMMC-related UPDs

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Phoenix doesn't have an eMMC controller and those UPDs were carried over
from Picasso. The SoC's fsp_m_params.c didn't write to any of those
fields, so this doesn't change any behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie3640c1493a92c1effba3ce42103d022bd8399ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held
2023-06-26 16:48:32 +02:00
parent c987d7b7d3
commit 5d65c819a9
1 changed files with 2 additions and 7 deletions
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9
src/vendorcode/amd/fsp/phoenix/FspmUpd.h
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@@ -78,12 +78,7 @@ typedef struct __packed {
/** Offset 0x041F**/ uint8_t audio_io_ctl; /** Offset 0x041F**/ uint8_t audio_io_ctl;
/** Offset 0x0420**/ uint8_t pdm_mic_selection; /** Offset 0x0420**/ uint8_t pdm_mic_selection;
/** Offset 0x0421**/ uint8_t hda_enable; /** Offset 0x0421**/ uint8_t hda_enable;
/** Offset 0x0422**/ uint8_t nbio_reserved[31]; /** Offset 0x0422**/ uint8_t nbio_reserved[40];
/** Offset 0x0441**/ uint32_t emmc0_mode;
/** Offset 0x0445**/ uint16_t emmc0_init_khz_preset;
/** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength;
/** Offset 0x0448**/ uint8_t emmc0_ddr50_driver_strength;
/** Offset 0x0449**/ uint8_t emmc0_sdr50_driver_strength;
/** Offset 0x044A**/ uint8_t UnusedUpdSpace0[85]; /** Offset 0x044A**/ uint8_t UnusedUpdSpace0[85];
/** Offset 0x049F**/ uint32_t gnb_ioapic_base; /** Offset 0x049F**/ uint32_t gnb_ioapic_base;
/** Offset 0x04A3**/ uint8_t gnb_ioapic_id; /** Offset 0x04A3**/ uint8_t gnb_ioapic_id;
@@ -112,7 +107,7 @@ typedef struct __packed {
#define IMAGE_REVISION_MAJOR_VERSION 0x01 #define IMAGE_REVISION_MAJOR_VERSION 0x01
#define IMAGE_REVISION_MINOR_VERSION 0x00 #define IMAGE_REVISION_MINOR_VERSION 0x00
#define IMAGE_REVISION_REVISION 0x05 #define IMAGE_REVISION_REVISION 0x06
#define IMAGE_REVISION_BUILD_NUMBER 0x00 #define IMAGE_REVISION_BUILD_NUMBER 0x00
#endif #endif