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mb/google/brox/jubilant: Update fw_config

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Change STORAGE_UNPROVISIONED to STORAGE_UNKNOWN depend on depthcharge setting.

BUG=None
TEST=emerge-brox coreboot
Set STORAGE_UNKNOWN  on jubilant, check that NVMe and UFS can boot.

Change-Id: I4cfd7322c2940862dfbae46e85522715cd7534c1
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83935
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
This commit is contained in:
Morris Hsu 2024-08-16 09:05:41 +08:00 committed by Felix Held
parent d9a625e052
commit 5d661b81ae
3 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/brox/variants/jubilant/fw_config.c
View File

@ -74,7 +74,7 @@ static void fw_config_handle(void *unused)
gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
} }
if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNPROVISIONED))) { if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
printk(BIOS_INFO, "Disable NVMe GPIO pins by fw_config.\n"); printk(BIOS_INFO, "Disable NVMe GPIO pins by fw_config.\n");
gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads));

8
src/mainboard/google/brox/variants/jubilant/overridetree.cb
View File

@ -1,8 +1,8 @@
fw_config fw_config
field STORAGE 2 3 field STORAGE 2 3
option STORAGE_UNKNOWN 0
option STORAGE_UFS 1 option STORAGE_UFS 1
option STORAGE_NVME 2 option STORAGE_NVME 2
option STORAGE_UNPROVISIONED 3
end end
field WIFI_BT 4 4 field WIFI_BT 4 4
option WIFI_BT_CNVI 0 option WIFI_BT_CNVI 0
@ -294,7 +294,7 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
}" }"
probe STORAGE STORAGE_NVME probe STORAGE STORAGE_NVME
probe STORAGE STORAGE_UNPROVISIONED probe STORAGE STORAGE_UNKNOWN
end end
device ref pcie_rp5 on device ref pcie_rp5 on
register "pch_pcie_rp[PCH_RP(5)]" = "{ register "pch_pcie_rp[PCH_RP(5)]" = "{
@ -332,11 +332,11 @@ chip soc/intel/alderlake
device generic 0 alias ish_conf on end device generic 0 alias ish_conf on end
end end
probe STORAGE STORAGE_UFS probe STORAGE STORAGE_UFS
probe STORAGE STORAGE_UNPROVISIONED probe STORAGE STORAGE_UNKNOWN
end end
device ref ufs on device ref ufs on
probe STORAGE STORAGE_UFS probe STORAGE STORAGE_UFS
probe STORAGE STORAGE_UNPROVISIONED probe STORAGE STORAGE_UNKNOWN
end end
device ref i2c0 on device ref i2c0 on
chip drivers/i2c/generic chip drivers/i2c/generic

2
src/mainboard/google/brox/variants/jubilant/variant.c
View File

@ -31,7 +31,7 @@ void variant_devtree_update(void)
struct device *ish = DEV_PTR(ish); struct device *ish = DEV_PTR(ish);
struct device *nvme_rp = DEV_PTR(pcie4_0); struct device *nvme_rp = DEV_PTR(pcie4_0);
if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNPROVISIONED))) { if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
printk(BIOS_INFO, "fw_config storage is unknown so enable all storage devices.\n"); printk(BIOS_INFO, "fw_config storage is unknown so enable all storage devices.\n");
return; return;
} }