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nb/intel/sandybridge: Rewrite constant values

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Rewrite some constants to make their meaning somewhat clearer.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: I321f5e61d7c695ae77e61b84728e34930f69d400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons
2020-12-13 16:37:53 +01:00
committed by Felix Held
parent 3170e9c0ef
commit 5db1b15147
4 changed files with 33 additions and 33 deletions
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2
src/northbridge/intel/sandybridge/raminit.c
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@ -309,7 +309,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
wait_txt_clear(); wait_txt_clear();
wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); wrmsr(0x2e6, (msr_t) { .lo = 0, .hi = 0 });
const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000 const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000
if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) { if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) {

44
src/northbridge/intel/sandybridge/raminit_common.c
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@ -44,7 +44,7 @@ static u32 get_XOVER_CMD(u8 rankmap)
u32 reg; u32 reg;
/* Enable xover cmd */ /* Enable xover cmd */
reg = 0x4000; reg = 1 << 14;
/* Enable xover ctl */ /* Enable xover ctl */
if (rankmap & 0x03) if (rankmap & 0x03)
@ -877,7 +877,7 @@ void dram_mrscommands(ramctr_timing *ctrl)
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = 0, .rank = 0,
@ -1145,7 +1145,7 @@ static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, i
FOR_ALL_LANES { FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].rcven ctrl->timings[channel][slotrank].lanes[lane].rcven
= upperA[lane] + rcven_delta + 0x40; = upperA[lane] + rcven_delta + 64;
} }
program_timings(ctrl, channel); program_timings(ctrl, channel);
@ -1234,7 +1234,7 @@ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank
printram("4028 += 2;\n"); printram("4028 += 2;\n");
/* Guard against I/O latency overflow */ /* Guard against I/O latency overflow */
if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { if (ctrl->timings[channel][slotrank].io_latency >= 16) {
printk(BIOS_EMERG, "I/O latency overflow: %d, %d\n", printk(BIOS_EMERG, "I/O latency overflow: %d, %d\n",
channel, slotrank); channel, slotrank);
return MAKE_ERR; return MAKE_ERR;
@ -1350,7 +1350,7 @@ int receive_enable_calibration(ramctr_timing *ctrl)
all_high = 1; all_high = 1;
some_high = 0; some_high = 0;
FOR_ALL_LANES { FOR_ALL_LANES {
if (ctrl->timings[channel][slotrank].lanes[lane].rcven >= 0x40) if (ctrl->timings[channel][slotrank].lanes[lane].rcven >= 64)
some_high = 1; some_high = 1;
else else
all_high = 0; all_high = 0;
@ -1360,8 +1360,8 @@ int receive_enable_calibration(ramctr_timing *ctrl)
ctrl->timings[channel][slotrank].io_latency--; ctrl->timings[channel][slotrank].io_latency--;
printram("4028--;\n"); printram("4028--;\n");
FOR_ALL_LANES { FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].rcven -= 0x40; ctrl->timings[channel][slotrank].lanes[lane].rcven -= 64;
upperA[lane] -= 0x40; upperA[lane] -= 64;
} }
} else if (some_high) { } else if (some_high) {
@ -1516,7 +1516,7 @@ static void program_wdb_pattern_length(int channel, const unsigned int num_cache
static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b)
{ {
unsigned int j; unsigned int j;
unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64;
for (j = 0; j < 16; j++) for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
@ -1537,8 +1537,8 @@ static int num_of_channels(const ramctr_timing *ctrl)
static void fill_pattern1(ramctr_timing *ctrl, int channel) static void fill_pattern1(ramctr_timing *ctrl, int channel)
{ {
unsigned int j; unsigned int j;
unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64;
unsigned int channel_step = 0x40 * num_of_channels(ctrl); unsigned int channel_step = 64 * num_of_channels(ctrl);
for (j = 0; j < 16; j++) for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
@ -1676,7 +1676,7 @@ static void train_write_flyby(ramctr_timing *ctrl)
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = slotrank, .rank = slotrank,
@ -1933,8 +1933,8 @@ static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank)
static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno)
{ {
unsigned int i, j; unsigned int i, j;
unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int offset = get_precedening_channels(ctrl, channel) * 64;
unsigned int step = 0x40 * num_of_channels(ctrl); unsigned int step = 64 * num_of_channels(ctrl);
if (patno) { if (patno) {
u8 base8 = 0x80 >> ((patno - 1) % 8); u8 base8 = 0x80 >> ((patno - 1) % 8);
@ -2218,8 +2218,8 @@ int read_mpr_training(ramctr_timing *ctrl)
* FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will
* also use a single loop. It would seem that it is a debugging configuration. * also use a single loop. It would seem that it is a debugging configuration.
*/ */
MCHBAR32(IOSAV_DC_MASK) = 0x300; MCHBAR32(IOSAV_DC_MASK) = 3 << 8;
printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
err = find_read_mpr_margin(ctrl, channel, slotrank, err = find_read_mpr_margin(ctrl, channel, slotrank,
@ -2228,8 +2228,8 @@ int read_mpr_training(ramctr_timing *ctrl)
return err; return err;
} }
MCHBAR32(IOSAV_DC_MASK) = 0x200; MCHBAR32(IOSAV_DC_MASK) = 2 << 8;
printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
err = find_read_mpr_margin(ctrl, channel, slotrank, err = find_read_mpr_margin(ctrl, channel, slotrank,
@ -2353,8 +2353,8 @@ int aggressive_read_training(ramctr_timing *ctrl)
* FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will
* also use a single loop. It would seem that it is a debugging configuration. * also use a single loop. It would seem that it is a debugging configuration.
*/ */
MCHBAR32(IOSAV_DC_MASK) = 0x300; MCHBAR32(IOSAV_DC_MASK) = 3 << 8;
printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
err = find_agrsv_read_margin(ctrl, channel, slotrank, err = find_agrsv_read_margin(ctrl, channel, slotrank,
@ -2363,8 +2363,8 @@ int aggressive_read_training(ramctr_timing *ctrl)
return err; return err;
} }
MCHBAR32(IOSAV_DC_MASK) = 0x200; MCHBAR32(IOSAV_DC_MASK) = 2 << 8;
printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
err = find_agrsv_read_margin(ctrl, channel, slotrank, err = find_agrsv_read_margin(ctrl, channel, slotrank,
@ -2971,7 +2971,7 @@ void restore_timings(ramctr_timing *ctrl)
MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0;
FOR_ALL_CHANNELS { FOR_ALL_CHANNELS {
MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24));
udelay(2); udelay(2);
} }
} }

14
src/northbridge/intel/sandybridge/raminit_iosav.c
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@ -94,7 +94,7 @@ void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap)
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = slotrank, .rank = slotrank,
@ -216,7 +216,7 @@ void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int sl
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = slotrank, .rank = slotrank,
@ -284,7 +284,7 @@ void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int sl
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = slotrank, .rank = slotrank,
@ -572,7 +572,7 @@ void iosav_write_command_training_sequence(
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = slotrank, .rank = slotrank,
@ -670,7 +670,7 @@ void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotr
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = slotrank, .rank = slotrank,
@ -765,7 +765,7 @@ void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = slotrank, .rank = slotrank,
@ -860,7 +860,7 @@ void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slot
.data_direction = SSQ_NA, .data_direction = SSQ_NA,
}, },
.sp_cmd_addr = { .sp_cmd_addr = {
.address = 1024, .address = 1 << 10,
.rowbits = 6, .rowbits = 6,
.bank = 0, .bank = 0,
.rank = slotrank, .rank = slotrank,

6
src/northbridge/intel/sandybridge/raminit_native.c
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@ -577,13 +577,13 @@ static void dram_freq(ramctr_timing *ctrl)
/* Step 2 - Select frequency in the MCU */ /* Step 2 - Select frequency in the MCU */
reg1 = ctrl->FRQ; reg1 = ctrl->FRQ;
if (ctrl->base_freq == 100) if (ctrl->base_freq == 100)
reg1 |= 0x100; /* Enable 100Mhz REF clock */ reg1 |= (1 << 8); /* Enable 100Mhz REF clock */
reg1 |= 0x80000000; /* set running bit */ reg1 |= (1 << 31); /* set running bit */
MCHBAR32(MC_BIOS_REQ) = reg1; MCHBAR32(MC_BIOS_REQ) = reg1;
int i = 0; int i = 0;
printk(BIOS_DEBUG, "PLL busy... "); printk(BIOS_DEBUG, "PLL busy... ");
while (reg1 & 0x80000000) { while (reg1 & (1 << 31)) {
udelay(10); udelay(10);
i++; i++;
reg1 = MCHBAR32(MC_BIOS_REQ); reg1 = MCHBAR32(MC_BIOS_REQ);