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soc/amd/phoenix: add openSIL calls

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Add the calls to the openSIL stubs to do the silicon initialization, to
get the APCI IO ports, and to get the memory map.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80296
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2024-02-01 20:24:34 +01:00
parent 2911823289
commit 5dc83818b8
3 changed files with 20 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/soc/amd/phoenix/acpi.c
View File

@@ -19,6 +19,7 @@
#include <device/device.h> #include <device/device.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <types.h> #include <types.h>
#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
#include "chip.h" #include "chip.h"
/* /*
@@ -29,12 +30,17 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{ {
const struct soc_amd_phoenix_config *cfg = config_of_soc(); const struct soc_amd_phoenix_config *cfg = config_of_soc();
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); if (CONFIG(PLATFORM_USES_FSP2_0)) {
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
fadt->gpe0_blk = ACPI_GPE0_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK;
} else {
/* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */
opensil_fill_fadt_io_ports(fadt);
}
fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_evt_len = 4; /* 32 bits */
fadt->pm1_cnt_len = 2; /* 16 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */

7
src/soc/amd/phoenix/chip.c
View File

@@ -12,6 +12,7 @@
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <types.h> #include <types.h>
#include <vendorcode/amd/opensil/stub/opensil.h>
#include "chip.h" #include "chip.h"
static const char *soc_acpi_name(const struct device *dev) static const char *soc_acpi_name(const struct device *dev)
@@ -39,8 +40,12 @@ static void soc_init(void *chip_info)
{ {
default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
if (CONFIG(PLATFORM_USES_FSP2_0)) if (CONFIG(PLATFORM_USES_FSP2_0)) {
amd_fsp_silicon_init(); amd_fsp_silicon_init();
} else {
setup_opensil();
opensil_xSIM_timepoint_1();
}
data_fabric_set_mmio_np(); data_fabric_set_mmio_np();

3
src/soc/amd/phoenix/memmap.c
View File

@@ -7,6 +7,7 @@
#include <cbmem.h> #include <cbmem.h>
#include <device/device.h> #include <device/device.h>
#include <stdint.h> #include <stdint.h>
#include <vendorcode/amd/opensil/stub/opensil.h>
/* /*
* +--------------------------------+ * +--------------------------------+
@@ -96,4 +97,6 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
if (CONFIG(PLATFORM_USES_FSP2_0)) if (CONFIG(PLATFORM_USES_FSP2_0))
read_fsp_resources(dev, idx); read_fsp_resources(dev, idx);
else
add_opensil_memmap(dev, idx);
} }