soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9838e2433004686e3ea82724c55066bcee1f019 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@@ -202,10 +202,10 @@ void soc_enable_psp_early(void);
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#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */
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#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */
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#define PSP_BAR_ENABLES 0x48
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#define PSP_BAR_ENABLES 0x48
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#define PSP_MAILBOX_BAR_EN 0x10
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#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
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#define PSP_MAILBOX_BAR_EN BIT(4)
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#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
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#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
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#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
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typedef struct aoac_devs {
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typedef struct aoac_devs {
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unsigned int :5;
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unsigned int :5;
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