sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions

Browse Source 
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM
Configuration

+-----------------------+-------------------------------+
|    Field Description  |       ASPM Support            |
+-----------------------+-------------------------------+
|     00b               |       No ASPM support         |
+-----------------------+-------------------------------+
|     01b               |       L0s Supported           |
+-----------------------+-------------------------------+
|     10b               |       L1 Supported            |
+-----------------------+-------------------------------+
|     11b               |       L0s and L1 Supported    |
+-----------------------+-------------------------------+

100b aka 0x4 is added by FSP to allow auto configuration (to avoid
conflicting with the PCI specification defined values).

Additionally, changed enum definition which is now meeting the FSP expectations better.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2022-12-13 14:10:48 +05:30
parent 0f15030700
commit 5dfec71829
2 changed files with 7 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View File

@@ -46,7 +46,6 @@ enum L1_substates_control {
/* This enum is for passing into an FSP UPD, typically ASPM */
enum ASPM_control {
ASPM_DEFAULT,
ASPM_DISABLE,
ASPM_L0S,
ASPM_L1,