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soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions

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As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM
Configuration

+-----------------------+-------------------------------+
|    Field Description  |       ASPM Support            |
+-----------------------+-------------------------------+
|     00b               |       No ASPM support         |
+-----------------------+-------------------------------+
|     01b               |       L0s Supported           |
+-----------------------+-------------------------------+
|     10b               |       L1 Supported            |
+-----------------------+-------------------------------+
|     11b               |       L0s and L1 Supported    |
+-----------------------+-------------------------------+

100b aka 0x4 is added by FSP to allow auto configuration (to avoid
conflicting with the PCI specification defined values).

Additionally, changed enum definition which is now meeting the FSP expectations better.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2022-12-13 14:10:48 +05:30
parent 0f15030700
commit 5dfec71829
2 changed files with 7 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/soc/intel/alderlake/fsp_params.c
View File

@@ -479,23 +479,18 @@ static int get_l1_substate_control(enum L1_substates_control ctl)
} }
/* /*
* Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
* a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
* that the mainboard setting does not disable ASPM incorrectly, chip
* config parameter values are offset by 1 with 0 meaning use FSP UPD default.
* get_aspm_control() ensures that the right UPD value is set in fsp_params. * get_aspm_control() ensures that the right UPD value is set in fsp_params.
* 0: Use FSP UPD default * 0: Disable ASPM
* 1: Disable ASPM * 1: L0s only
* 2: L0s only * 2: L1 only
* 3: L1 only * 3: L0s and L1
* 4: L0s and L1 * 4: Auto configuration
* 5: Auto configuration
*/ */
static unsigned int get_aspm_control(enum ASPM_control ctl) static unsigned int get_aspm_control(enum ASPM_control ctl)
{ {
if ((ctl > ASPM_AUTO) || (ctl == ASPM_DEFAULT)) if (ctl > ASPM_AUTO)
ctl = ASPM_AUTO; ctl = ASPM_AUTO;
return ctl - 1; return ctl;
} }
/* This function returns the VccIn Aux Imon IccMax values for ADL and RPL /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL

1
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View File

@@ -46,7 +46,6 @@ enum L1_substates_control {
/* This enum is for passing into an FSP UPD, typically ASPM */ /* This enum is for passing into an FSP UPD, typically ASPM */
enum ASPM_control { enum ASPM_control {
ASPM_DEFAULT,
ASPM_DISABLE, ASPM_DISABLE,
ASPM_L0S, ASPM_L0S,
ASPM_L1, ASPM_L1,