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mb/intel/saddlebrook: migrate to FSP 2.0

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This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.

The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:

- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)

TODO:
- testing

Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923
Reviewed-by: Michael Niewöhner
Reviewed-by: Wim Vervoorn
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner
2019-10-09 21:02:36 +02:00
committed by Nico Huber
parent fda6cd6d28
commit 5e779f9a6c
4 changed files with 69 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/intel/saddlebrook/Kconfig
View File

@@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_CMOS_DEFAULT select HAVE_CMOS_DEFAULT
select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_USES_IFD_GBE_REGION
select USE_INTEL_FSP_MP_INIT select USE_INTEL_FSP_MP_INIT
select MAINBOARD_USES_FSP2_0
config IRQ_SLOT_COUNT config IRQ_SLOT_COUNT
int int

120
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@@ -61,82 +61,70 @@ chip soc/intel/skylake
register "serirq_mode" = "SERIRQ_CONTINUOUS" register "serirq_mode" = "SERIRQ_CONTINUOUS"
# VR Settings Configuration for 5 Domains # VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------------+-------------+-------+ #+----------------+-----------+-----------+-------------+----------+
#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | #| Domain/Setting | SA | IA | GT Unsliced | GT |
#+----------------+-------+-------+-------------+-------------+-------+ #+----------------+-----------+-----------+-------------+----------+
#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | #| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | #| Psi2Threshold | 4A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | #| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 | 1 | #| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 7A | 34A | 34A | 35A | 35A | #| IccMax | 7A | 34A | 35A | 35A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------------+-------------+-------+ #+----------------+-----------+-----------+-------------+----------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \ .vr_config_enable = 1,
.psi1threshold = 0x50, \ .psi1threshold = VR_CFG_AMP(20),
.psi2threshold = 0x10, \ .psi2threshold = VR_CFG_AMP(4),
.psi3threshold = 0x4, \ .psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1, \ .psi3enable = 1,
.psi4enable = 1, \ .psi4enable = 1,
.imon_slope = 0x0, \ .imon_slope = 0x0,
.imon_offset = 0x0, \ .imon_offset = 0x0,
.icc_max = 0x1C, \ .icc_max = VR_CFG_AMP(7),
.voltage_limit = 0x5F0 \ .voltage_limit = 1520,
}" }"
register "domain_vr_config[VR_IA_CORE]" = "{ register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1, \ .vr_config_enable = 1,
.psi1threshold = 0x50, \ .psi1threshold = VR_CFG_AMP(20),
.psi2threshold = 0x14, \ .psi2threshold = VR_CFG_AMP(5),
.psi3threshold = 0x4, \ .psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1, \ .psi3enable = 1,
.psi4enable = 1, \ .psi4enable = 1,
.imon_slope = 0x0, \ .imon_slope = 0x0,
.imon_offset = 0x0, \ .imon_offset = 0x0,
.icc_max = 0x88, \ .icc_max = VR_CFG_AMP(34),
.voltage_limit = 0x5F0 \ .voltage_limit = 1520,
}"
register "domain_vr_config[VR_RING]" = "{
.vr_config_enable = 1, \
.psi1threshold = 0x50, \
.psi2threshold = 0x14, \
.psi3threshold = 0x4, \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0x0, \
.imon_offset = 0x0, \
.icc_max = 0x88, \
.voltage_limit = 0x5F0, \
}" }"
register "domain_vr_config[VR_GT_UNSLICED]" = "{ register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1, \ .vr_config_enable = 1,
.psi1threshold = 0x50, \ .psi1threshold = VR_CFG_AMP(20),
.psi2threshold = 0x14, \ .psi2threshold = VR_CFG_AMP(5),
.psi3threshold = 0x4, \ .psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1, \ .psi3enable = 1,
.psi4enable = 1, \ .psi4enable = 1,
.imon_slope = 0x0, \ .imon_slope = 0x0,
.imon_offset = 0x0, \ .imon_offset = 0x0,
.icc_max = 0x8C ,\ .icc_max = VR_CFG_AMP(35),
.voltage_limit = 0x5F0 \ .voltage_limit = 1520,
}" }"
register "domain_vr_config[VR_GT_SLICED]" = "{ register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1, \ .vr_config_enable = 1,
.psi1threshold = 0x50, \ .psi1threshold = VR_CFG_AMP(20),
.psi2threshold = 0x14, \ .psi2threshold = VR_CFG_AMP(5),
.psi3threshold = 0x4, \ .psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1, \ .psi3enable = 1,
.psi4enable = 1, \ .psi4enable = 1,
.imon_slope = 0x0, \ .imon_slope = 0x0,
.imon_offset = 0x0, \ .imon_offset = 0x0,
.icc_max = 0x8C, \ .icc_max = VR_CFG_AMP(35),
.voltage_limit = 0x5F0 \ .voltage_limit = 1520,
}" }"
# Enable x1 slot # Enable x1 slot

2
src/mainboard/intel/saddlebrook/ramstage.c
View File

@@ -16,7 +16,7 @@
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include "gpio.h" #include "gpio.h"
void mainboard_silicon_init_params(SILICON_INIT_UPD *params) void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{ {
/* Configure pads prior to SiliconInit() in case there's any /* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */ * dependencies during hardware initialization. */

30
src/mainboard/intel/saddlebrook/romstage.c
View File

@@ -24,10 +24,10 @@
#include <spd_bin.h> #include <spd_bin.h>
void mainboard_memory_init_params( void mainboard_memory_init_params(FSPM_UPD *mupd)
struct romstage_params *params,
MEMORY_INIT_UPD *memory_params)
{ {
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
struct spd_block blk = { struct spd_block blk = {
.addr_map = { 0x50, 0x52, }, .addr_map = { 0x50, 0x52, },
}; };
@@ -36,26 +36,22 @@ void mainboard_memory_init_params(
dump_spd_info(&blk); dump_spd_info(&blk);
printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len); printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len);
memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; mem_cfg->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1]; mem_cfg->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", mem_cfg->MemorySpdPtr00);
memory_params->MemorySpdPtr00); printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", mem_cfg->MemorySpdPtr10);
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
memory_params->MemorySpdPtr10);
/* /*
* Configure the DQ/DQS settings if required. In general the settings * Configure the DQ/DQS settings if required. In general the settings
* should be set in the FSP flash image and should not need to be * should be set in the FSP flash image and should not need to be
* changed. * changed.
*/ */
mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1);
&memory_params->DqByteMapCh1); mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1);
mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
mainboard_fill_rcomp_res_data(&memory_params->RcompResistor);
mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget);
/* update spd length*/ /* update spd length*/
memory_params->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdDataLen = blk.len;
memory_params->DqPinsInterleaved = TRUE; mem_cfg->DqPinsInterleaved = TRUE;
} }