Whitespace changes to make s2912_fam10/ms9652_fam10 more similar.

Also, fix another typo in the ms9652 board name.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-03-01 20:16:38 +00:00
parent d71e771081
commit 5fa76e2864
8 changed files with 39 additions and 46 deletions

View File

@@ -134,7 +134,7 @@ config LB_CKS_LOC
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string
default "MS-9252" default "MS-9652"
depends on BOARD_MSI_MS9652_FAM10 depends on BOARD_MSI_MS9652_FAM10
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID

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@@ -153,7 +153,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
@@ -165,8 +164,6 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0); dword |= (1<<0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
} }
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)

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@@ -19,7 +19,7 @@
/** /**
* This file defines the SPD addresses for the mainboard. Must be included in * This file defines the SPD addresses for the mainboard. Must be included in
* cache_as_ram_auto.c * romstage.c
*/ */
#define RC00 0 #define RC00 0

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@@ -68,7 +68,6 @@ static unsigned get_bus_conf_done = 0;
void get_bus_conf(void) void get_bus_conf(void)
{ {
unsigned apicid_base; unsigned apicid_base;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
@@ -134,5 +133,4 @@ void get_bus_conf(void)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS; apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif #endif
m->apicid_mcp55 = apicid_base+0; m->apicid_mcp55 = apicid_base+0;
} }

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@@ -150,10 +150,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;