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Whitespace changes to make s2912_fam10/ms9652_fam10 more similar.

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Also, fix another typo in the ms9652 board name.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-03-01 20:16:38 +00:00
parent d71e771081
commit 5fa76e2864
8 changed files with 39 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/msi/ms9652_fam10/Kconfig
View File

@@ -134,7 +134,7 @@ config LB_CKS_LOC
config MAINBOARD_PART_NUMBER
string
default "MS-9252"
default "MS-9652"
depends on BOARD_MSI_MS9652_FAM10
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID

23
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@@ -50,9 +50,9 @@
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
static void post_code(u8 value) {
static void post_code(u8 value) {
outb(value, 0x80);
}
}
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "arch/i386/lib/console.c"
@@ -153,7 +153,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
@@ -165,8 +164,6 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
}
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -281,10 +278,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
val = cpuid_eax(1);
printk_debug("BSP Family_Model: %08x \n", val);
printk_debug("BSP Family_Model: %08x\n", val);
printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
printk_debug("bsp_apicid = %02x \n", bsp_apicid);
printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
printk_debug("bsp_apicid = %02x\n", bsp_apicid);
printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -300,12 +297,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup nodes PCI space and start core 0 AP init. */
finalize_node_setup(sysinfo);
printk_debug("finalize_node_setup done \n");
printk_debug("finalize_node_setup done\n");
/* Setup any mainboard PCI settings etc. */
printk_debug("setup_mb_resource_map begin \n");
printk_debug("setup_mb_resource_map begin\n");
setup_mb_resource_map();
printk_debug("setup_mb_resource_map end \n");
printk_debug("setup_mb_resource_map end\n");
post_code(0x36);
/* wait for all the APs core0 started by finalize_node_setup. */
@@ -329,7 +326,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if FAM10_SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
* need to be done once.*/
@@ -347,7 +344,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
wants_reset = mcp55_early_setup_x();

2
src/mainboard/msi/ms9652_fam10/spd_addr.h
View File

@@ -19,7 +19,7 @@
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* cache_as_ram_auto.c
* romstage.c
*/
#define RC00 0

2
src/mainboard/tyan/s2912_fam10/get_bus_conf.c
View File

@@ -68,7 +68,6 @@ static unsigned get_bus_conf_done = 0;
void get_bus_conf(void)
{
unsigned apicid_base;
struct mb_sysconf_t *m;
@@ -134,5 +133,4 @@ void get_bus_conf(void)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
m->apicid_mcp55 = apicid_base+0;
}

12
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@@ -150,10 +150,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
@@ -278,10 +276,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
val = cpuid_eax(1);
printk_debug("BSP Family_Model: %08x \n", val);
printk_debug("BSP Family_Model: %08x\n", val);
printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
printk_debug("bsp_apicid = %02x \n", bsp_apicid);
printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
printk_debug("bsp_apicid = %02x\n", bsp_apicid);
printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -322,7 +320,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if FAM10_SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
* need to be done once.*/
@@ -340,7 +338,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
wants_reset = mcp55_early_setup_x();