get include files right

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
2005-10-19 20:32:05 +00:00
parent a83620fda3
commit 5fc3aa73eb
4 changed files with 1424 additions and 13 deletions

View File

@ -3,17 +3,13 @@
##
uses _RAMBASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
##
## Use cache ram for initial setup
## Assumes RAM already initialiazed
## This is true for the Apache board, but may
## not be for other 970 systems.
##
default USE_DCACHE_RAM=1
## Set dcache ram above linuxbios image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 32Kb
default DCACHE_RAM_SIZE=0x8000
default USE_DCACHE_RAM=0
initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc

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@ -29,9 +29,7 @@
| 10-Feb-04 Port to PPC970FX MPT
+----------------------------------------------------------------------------*/
#include <sys/as_archppc.h>
#include <sys/as_archppc970.h>
#include <ppc970fx_board.h>
#include <ppc970.h>
/*----------------------------------------------------------------------------+
| Local defines.
@ -44,7 +42,6 @@
| Init_core. Assumption: hypervisor on, 64-bit on, HID1[10]=0, HID4[23]=0.
| Data cahability must be turned on. Instruction cahability must be off.
+----------------------------------------------------------------------------*/
function_prolog(init_core)
/*--------------------------------------------------------------------+
| Set time base to 0.
+--------------------------------------------------------------------*/
@ -366,4 +363,3 @@ function_prolog(init_core)
eieio
mtspr SPR_SRR0,r0
rfid
function_epilog(init_core)