riscv: add support for modifying compiler options

Each HART of a SoC like fu540 supports a different ISA. In order for the
coreboot's code can run on each core, need to modify the compile options. 
So add this code.

Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>

src/soc/lowrisc/lowrisc/Kconfig

@@ -11,4 +11,16 @@ config SOC_LOWRISC_LOWRISC
 
 if SOC_LOWRISC_LOWRISC
 
+config RISCV_ARCH
+	string
+	default "rv64imafd"
+
+config RISCV_ABI
+	string
+	default "lp64d"
+
+config RISCV_CODEMODEL
+	string
+	default "medany"
+
 endif

src/soc/sifive/fu540/Kconfig

@@ -23,4 +23,16 @@ config SOC_SIFIVE_FU540
 
 if SOC_SIFIVE_FU540
 
+config RISCV_ARCH
+	string
+	default "rv64imac"
+
+config RISCV_ABI
+	string
+	default "lp64"
+
+config RISCV_CODEMODEL
+	string
+	default "medany"
+
 endif

src/soc/ucb/riscv/Kconfig

@@ -10,4 +10,16 @@ config SOC_UCB_RISCV
 
 if SOC_UCB_RISCV
 
+config RISCV_ARCH
+	string
+	default "rv64imafd"
+
+config RISCV_ABI
+	string
+	default "lp64d"
+
+config RISCV_CODEMODEL
+	string
+	default "medany"
+
 endif