util/inteltool: Add pci ids for 4 northbridge models instead of 1.
This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core. Tested on 0x0150 (0x0154 previously only model). Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5873 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Idwer Vollering
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0240f9492b
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601da481b5
@@ -154,7 +154,10 @@
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#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
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#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
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#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A 0x0150 /* Ivy Bridge */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B 0x0154 /* Ivy Bridge */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C 0x0158 /* Ivy Bridge */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x015c /* Ivy Bridge */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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