util/inteltool: Add pci ids for 4 northbridge models instead of 1.
This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core. Tested on 0x0150 (0x0154 previously only model). Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5873 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Idwer Vollering
parent
0240f9492b
commit
601da481b5
@@ -251,7 +251,10 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
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mch_registers = sandybridge_mch_registers;
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size = ARRAY_SIZE(sandybridge_mch_registers);
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
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mchbar_phys = pci_read_long(nb, 0x48);
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
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