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soc/amd: introduce and use common IOAPIC IDs

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Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.

Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2021-02-12 00:43:20 +01:00
parent 5f5b7ddbf3
commit 604ffa6d23
9 changed files with 27 additions and 37 deletions
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18
src/soc/amd/picasso/Kconfig
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@@ -238,24 +238,6 @@ config HEAP_SIZE
hex
default 0xc0000
config PICASSO_FCH_IOAPIC_ID
hex
default 0x8
help
The Picasso APU has two IOAPICs, one in the FCH and one in the
northbridge. Set this value for the intended ID to assign to the
FCH IOAPIC. The value should be >= MAX_CPUS and different from
the GNB's IOAPIC_ID.
config PICASSO_GNB_IOAPIC_ID
hex
default 0x9
help
The Picasso APU has two IOAPICs, one in the FCH and one in the
northbridge. Set this value for the intended ID to assign to the
GNB IOAPIC. The value should be >= MAX_CPUS and different from
the FCH's IOAPIC_ID.
config SERIRQ_CONTINUOUS_MODE
bool
default n