intel/common/block/smm: Update smihandler to handle gpi

Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.

Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/apollolake/include/soc/smm.h

@@ -30,7 +30,4 @@
 void southbridge_smm_clear_state(void);
 void southbridge_smm_enable_smi(void);
 
-/* Mainboard handler for GPI SMIs*/
-void mainboard_smi_gpi_handler(const struct gpi_status *sts);
-
 #endif

src/soc/intel/apollolake/smihandler.c

@@ -34,26 +34,11 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void)
 	return &em64t100_smm_ops;
 }
 
-void __attribute__((weak))
-mainboard_smi_gpi_handler(const struct gpi_status *sts) { }
-
-static void southbridge_smi_gpi(
-	const struct smm_save_state_ops *save_state_ops)
-{
-	struct gpi_status smi_sts;
-
-	gpi_clear_get_smi_status(&smi_sts);
-	mainboard_smi_gpi_handler(&smi_sts);
-
-	/* Clear again after mainboard handler */
-	gpi_clear_get_smi_status(&smi_sts);
-}
-
 const smi_handler_t southbridge_smi[32] = {
 	[SLP_SMI_STS] = smihandler_southbridge_sleep,
 	[APM_SMI_STS] = smihandler_southbridge_apmc,
 	[FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1,
-	[GPIO_SMI_STS] = southbridge_smi_gpi,
+	[GPIO_SMI_STS] = smihandler_southbridge_gpi,
 	[TCO_SMI_STS] = smihandler_southbridge_tco,
 	[PERIODIC_SMI_STS] = smihandler_southbridge_periodic,
 };