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soc/intel/tigerlake: Update Tiger Lake SA IDs

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This patch updates Tiger Lake SA DID and report platform. According to
doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below
definitions of SA ID for TGL-UP4 skus:
TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h
TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h

Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Derek Huang
2020-07-03 15:33:13 +08:00
committed by Tim Wawrzynczak
parent 0b5a6143ea
commit 60f178db65
4 changed files with 12 additions and 13 deletions
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6
src/include/device/pci_ids.h
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@@ -3521,10 +3521,10 @@
#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
#define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2 0x9A14
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12
#define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532
#define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
#define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22