armv7: import updated cache/MMU stuff from coreboot
This imports the cache/MMU code from coreboot as of 1877cee
.
Change-Id: I97ec8b9640921a94a4b27d89e4ae6185e9f96f18
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/48288
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4134
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
committed by
Stefan Reinauer
parent
7905f9254e
commit
6119bea233
@@ -31,7 +31,7 @@
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* Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
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*/
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#include <inttypes.h>
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#include <stdint.h>
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#include <arch/cache.h>
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@@ -149,14 +149,39 @@ static void dcache_op_set_way(enum dcache_op op)
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isb();
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}
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static void dcache_foreach(enum dcache_op op)
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{
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uint32_t clidr;
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int level;
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clidr = read_clidr();
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for (level = 0; level < 7; level++) {
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unsigned int ctype = (clidr >> (level * 3)) & 0x7;
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uint32_t csselr;
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switch(ctype) {
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case 0x2:
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case 0x3:
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case 0x4:
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csselr = level << 1;
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write_csselr(csselr);
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dcache_op_set_way(op);
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break;
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default:
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/* no cache, icache only, or reserved */
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break;
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}
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}
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}
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void dcache_clean_invalidate_all(void)
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{
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dcache_op_set_way(OP_DCCISW);
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dcache_foreach(OP_DCCISW);
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}
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void dcache_invalidate_all(void)
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{
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dcache_op_set_way(OP_DCISW);
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dcache_foreach(OP_DCISW);
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}
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static unsigned int line_bytes(void)
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@@ -212,15 +237,9 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
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void dcache_mmu_disable(void)
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{
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uint32_t sctlr, csselr;
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/* ensure L1 data/unified cache is selected */
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csselr = read_csselr();
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csselr &= ~0xf;
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write_csselr(csselr);
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uint32_t sctlr;
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dcache_clean_invalidate_all();
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sctlr = read_sctlr();
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sctlr &= ~(SCTLR_C | SCTLR_M);
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write_sctlr(sctlr);
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@@ -264,6 +283,8 @@ void armv7_invalidate_caches(void)
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case 0x2:
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case 0x4:
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/* dcache only or unified cache */
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csselr = level << 1;
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write_csselr(csselr);
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dcache_invalidate_all();
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break;
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case 0x3:
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@@ -272,7 +293,7 @@ void armv7_invalidate_caches(void)
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write_csselr(csselr);
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icache_invalidate_all();
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csselr = level < 1;
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csselr = level << 1;
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write_csselr(csselr);
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dcache_invalidate_all();
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break;
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