sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

armv7: import updated cache/MMU stuff from coreboot

Browse Source 
This imports the cache/MMU code from coreboot as of 1877cee.

Change-Id: I97ec8b9640921a94a4b27d89e4ae6185e9f96f18
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/48288
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4134
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks
2013-03-29 13:24:29 -07:00
committed by Stefan Reinauer
parent 7905f9254e
commit 6119bea233
2 changed files with 54 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
payloads/libpayload/include/armv7/arch/cache.h
View File

@ -219,10 +219,29 @@ static inline void write_csselr(uint32_t val)
isb(); /* ISB to sync the change to CCSIDR */
}
/* read system control register (SCTLR) */
static inline unsigned int read_sctlr(void)
/* read L2 control register (L2CTLR) */
static inline uint32_t read_l2ctlr(void)
{
unsigned int val;
uint32_t val = 0;
asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
return val;
}
/* write L2 control register (L2CTLR) */
static inline void write_l2ctlr(uint32_t val)
{
/*
* Note: L2CTLR can only be written when the L2 memory system
* is idle, ie before the MMU is enabled.
*/
asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
isb();
}
/* read system control register (SCTLR) */
static inline uint32_t read_sctlr(void)
{
uint32_t val;
asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
return val;
}