Move gpio.h to gpio.c on sandy and ivy.
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13657 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
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Martin Roth
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@ -42,3 +42,4 @@ $(SPD_BIN): $(SPD_DEPS)
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cbfs-files-y += spd.bin
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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spd.bin-type := spd
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romstage-y += gpio.c
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@ -29,13 +29,12 @@
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#include <console/console.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include "ec/google/chromeec/ec.h"
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#include "ec/google/chromeec/ec.h"
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <halt.h>
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#include "gpio.h"
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#include <tpm.h>
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#include <tpm.h>
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#include <cbfs.h>
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#include <cbfs.h>
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@ -17,3 +17,4 @@ ramstage-y += ec.c
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romstage-y += chromeos.c
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romstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-y += chromeos.c
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romstage-y += gpio.c
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@ -29,11 +29,9 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <halt.h>
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#include "gpio.h"
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#include <cbfs.h>
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#include <cbfs.h>
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#include <tpm.h>
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#include <tpm.h>
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#include "ec/compal/ene932/ec.h"
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#include "ec/compal/ene932/ec.h"
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@ -22,3 +22,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c
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SRC_ROOT = $(src)/mainboard/google/stout
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SRC_ROOT = $(src)/mainboard/google/stout
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romstage-y += gpio.c
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@ -29,11 +29,9 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <halt.h>
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#include "gpio.h"
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#include <bootmode.h>
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#include <bootmode.h>
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#include <tpm.h>
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#include <tpm.h>
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#include <cbfs.h>
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#include <cbfs.h>
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@ -15,3 +15,4 @@
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romstage-y += chromeos.c
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romstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-y += chromeos.c
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romstage-y += gpio.c
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@ -30,12 +30,10 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <halt.h>
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#include <tpm.h>
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#include <tpm.h>
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#include "gpio.h"
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#define SIO_PORT 0x164e
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#define SIO_PORT 0x164e
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1
src/mainboard/kontron/ktqm77/Makefile.inc
Normal file
1
src/mainboard/kontron/ktqm77/Makefile.inc
Normal file
@ -0,0 +1 @@
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romstage-y += gpio.c
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@ -29,11 +29,9 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <halt.h>
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#include "gpio.h"
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void pch_enable_lpc(void)
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void pch_enable_lpc(void)
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{
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{
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@ -27,3 +27,4 @@ $(SPD_BIN):
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cbfs-files-y += spd.bin
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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spd.bin-type := spd
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romstage-y += gpio.c
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@ -32,12 +32,10 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <halt.h>
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#include "option_table.h"
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#include "option_table.h"
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#include "gpio.h"
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#if CONFIG_DRIVERS_UART_8250IO
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#if CONFIG_DRIVERS_UART_8250IO
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#include <superio/smsc/lpc47n207/lpc47n207.h>
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#include <superio/smsc/lpc47n207/lpc47n207.h>
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#endif
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#endif
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@ -15,3 +15,4 @@
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romstage-y += chromeos.c
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romstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-y += chromeos.c
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romstage-y += gpio.c
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@ -32,12 +32,10 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <halt.h>
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#include <tpm.h>
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#include <tpm.h>
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#include "gpio.h"
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#if CONFIG_DRIVERS_UART_8250IO
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#if CONFIG_DRIVERS_UART_8250IO
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#include <superio/smsc/lpc47n207/lpc47n207.h>
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#include <superio/smsc/lpc47n207/lpc47n207.h>
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#endif
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#endif
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