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drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S

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soc/car_setup.S is included when SKIP_FSP_CAR is enabled,
but no chipset/SoC have car_setup.S available.
Remove include and post_code() call always solving build errors.

BUG=NA
TEST=NA

Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
This commit is contained in:
Frans Hendriks
2018-11-19 11:59:00 +01:00
committed by Patrick Georgi
parent 166cbdec5b
commit 613da18fec
1 changed files with 0 additions and 13 deletions
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13
src/drivers/intel/fsp1_1/cache_as_ram.inc
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@@ -37,19 +37,6 @@
cache_as_ram: cache_as_ram:
post_code(0x20) post_code(0x20)
#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
/*
* SOC specific setup
* NOTE: This has to preserve the registers
* mm0, mm1 and edi.
*/
#include <soc/car_setup.S>
post_code(0x28)
#endif
/* /*
* Find the FSP binary in cbfs. * Find the FSP binary in cbfs.
* Make a fake stack that has the return value back to this code. * Make a fake stack that has the return value back to this code.