From 61a442ec01b1a7d9a2d83604956f8355ea391b3e Mon Sep 17 00:00:00 2001 From: Cliff Huang Date: Thu, 28 Apr 2022 18:06:54 -0700 Subject: [PATCH] soc/intel/alderlake: Add support for PCIe slot & device detect timeout 1. add timeout for root port detection and pass to FSP. 2. add 'slot implemented' flag and pass to FSP. 3. PcieRpSlotImplemented needs to be set when the root port is set to hotplug. There is an assertion in FSP checking this. 4. PcieRpSlotImplemented is updated only when it is built-in as it is default to slot implemented in FSP. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Anil Kumar K Reviewed-by: Eric Lai --- src/soc/intel/alderlake/fsp_params.c | 4 ++++ src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index e3222be02e..f14adbdc83 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -673,6 +673,10 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); if (rp_cfg->pcie_rp_aspm) s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); + /* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */ + if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) + s_cfg->PcieRpSlotImplemented[i] = 0; + s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; } } diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 66ced7ee46..9832feb83f 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -27,6 +27,8 @@ enum pcie_rp_flags { PCIE_RP_CLK_REQ_DETECT = (1 << 4), /* Clock request signal is not used by the root port. */ PCIE_RP_CLK_REQ_UNUSED = (1 << 5), + /* indicates that this root port is built-in. */ + PCIE_RP_BUILT_IN = (1 << 6), }; enum pcie_clk_src_flags { @@ -63,6 +65,8 @@ struct pcie_rp_config { enum L1_substates_control PcieRpL1Substates; /* PCIe RP ASPM */ enum ASPM_control pcie_rp_aspm; + /* timeout for device detect */ + uint32_t pcie_rp_detect_timeout_ms; }; /*