mb/google/ovis/var/deku: Set PsysPL2 value to 178W

Adjust setting as recommended by power team.
Add ramstage.c in Makefile.inc to set psys_pl2_watts in
variant_devtree_update().

Also copy CPU power limit values from ovis baseboard.

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
     check overrides setting
     [INFO] CPU PsysPL2 = 178 Watts
     [INFO] Overriding PsysPL2 (178)
     [INFO] Overriding power limits PL1 (mW) (19000,28000) PL2 (mW)
     (64000, 64000) PL4 (W) (120)

Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>

src/mainboard/google/rex/variants/deku/Makefile.mk

@@ -3,3 +3,4 @@
 bootblock-y += gpio.c
 romstage-y += gpio.c
 ramstage-y += gpio.c
+ramstage-y += ramstage.c

src/mainboard/google/rex/variants/deku/overridetree.cb

@@ -64,6 +64,7 @@ chip soc/intel/meteorlake
 	}"
 
 	register "psys_pmax_watts" = "180"
+	register "psys_pl2_watts"  = "178"
 
 	# As per doc 640982, Intel MTL-U 28W CPU supports FVM on GT and SA
 	# The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A

src/mainboard/google/rex/variants/deku/ramstage.c

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <intelblocks/power_limit.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+const struct cpu_tdp_power_limits variant_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_1,
+		.cpu_tdp = 28,
+		.pl1_min_power = 19000,
+		.pl1_max_power = 28000,
+		.pl2_min_power = 64000,
+		.pl2_max_power = 64000,
+		.pl4_power = 120000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_3,
+		.cpu_tdp = 28,
+		.pl1_min_power = 19000,
+		.pl1_max_power = 28000,
+		.pl2_min_power = 64000,
+		.pl2_max_power = 64000,
+		.pl4_power = 120000
+	},
+};
+
+void variant_devtree_update(void)
+{
+	struct soc_power_limits_config *soc_config;
+	struct soc_intel_meteorlake_config *config = config_of_soc();
+
+	soc_config = variant_get_soc_power_limit_config();
+	if (soc_config == NULL)
+		return;
+
+	if (config->psys_pl2_watts) {
+		soc_config->tdp_psyspl2 = config->psys_pl2_watts;
+		printk(BIOS_INFO, "Overriding PsysPL2 (%u)\n", soc_config->tdp_psyspl2);
+	}
+
+	const struct cpu_tdp_power_limits *limits = variant_limits;
+	size_t total_entries = ARRAY_SIZE(variant_limits);
+	variant_update_cpu_power_limits(limits, total_entries);
+}