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mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)

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1. Ref to SCH, LTE use USB3 Port3, enable it.
2. Explicitly define the use of USB3 Port1 & USB3 Port2.

BUG=b:315061146
TEST=can pass PCIe Hardware Compliance Test

Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Weimin Wu
2023-12-08 10:58:20 +08:00
committed by Felix Held
parent 133e3ee661
commit 6215ef47cd
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/brya/variants/anraggar/overridetree.cb
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@@ -416,6 +416,10 @@ chip soc/intel/alderlake
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch) register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for CNVi WLAN register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB))
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
chip drivers/usb/acpi chip drivers/usb/acpi
device ref xhci_root_hub on device ref xhci_root_hub on
chip drivers/usb/acpi chip drivers/usb/acpi