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Documentation: Fix toctree and remove dead links

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Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph
2021-01-11 08:52:50 +01:00
committed by Patrick Georgi
parent fc1d50a365
commit 6279cabb5b
4 changed files with 4 additions and 6 deletions
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5
Documentation/soc/intel/icelake/iceLake_coreboot_development.md
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@@ -20,11 +20,6 @@ Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel
:doc:`../../../mainboard/intel/icelake_rvp`
```
3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google
```eval_rst
:doc:`../../../mainboard/google/dragonegg`
```
### Summary:
* SoC is Ice Lake.
* Reference platform is icelake_rvp.

2
Documentation/soc/intel/index.md
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@@ -11,4 +11,4 @@ This section contains documentation about coreboot on specific Intel SOCs.
- [Microcode Updates](microcode.md)
- [Firmware Interface Table](fit.md)
- [Apollolake](apollolake/index.md)
- [CSE FW Update](cse_fw_update/cse_fw_update_model.md)
- [CSE FW Update](cse_fw_update/cse_fw_update.md)