ChangeLog:
Add initial ACPI support for M57SLI. Activates/Enables: * native Coreboot ACPI for M57SLI * Soft-Power-Off * PowerNow! * High Precision Event Timer * Windows booting with ACPI support Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Harald Gutmann
@@ -19,6 +19,8 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses HAVE_ACPI_TABLES
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config chip.h
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driver mcp55.o
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driver mcp55_usb.o
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@@ -33,3 +35,6 @@ driver mcp55_pci.o
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driver mcp55_pcie.o
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driver mcp55_ht.o
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object mcp55_reset.o
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if HAVE_ACPI_TABLES
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object mcp55_fadt.o
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end
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173
src/southbridge/nvidia/mcp55/mcp55_fadt.c
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173
src/southbridge/nvidia/mcp55/mcp55_fadt.c
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@@ -0,0 +1,173 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci_ids.h>
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extern unsigned pm_base;
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/* Create the Fixed ACPI Description Tables (FADT) for this board. */
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void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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{
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acpi_header_t *header = &(fadt->header);
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device_t dev;
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int is_mcp55 = 0;
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dev = dev_find_device(PCI_VENDOR_ID_NVIDIA,
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PCI_DEVICE_ID_NVIDIA_MCP55_LPC, 0);
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if (dev)
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is_mcp55 = 1;
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memset((void *) fadt, 0, sizeof(acpi_fadt_t));
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memcpy(header->signature, "FACP", 4);
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header->length = sizeof(acpi_fadt_t);
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header->revision = 1;
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memcpy(header->oem_id, "GBT", 6);
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memcpy(header->oem_table_id, "COREBOOT ", 8);
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memcpy(header->asl_compiler_id, "CORE", 4);
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header->asl_compiler_revision = 42;
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printk_info("ACPI: pm_base: %u...\n", pm_base);
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fadt->firmware_ctrl = facs;
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fadt->dsdt = dsdt;
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fadt->preferred_pm_profile = 1; //check
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fadt->sci_int = 9;
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/* disable system management mode by setting to 0 */
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fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt)
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fadt->acpi_enable = 0xa1;
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fadt->acpi_disable = 0xa0;
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0x0;
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fadt->pm1a_evt_blk = pm_base;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pm_base + 0x4;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->pm2_cnt_blk = pm_base + 0x1c;
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fadt->pm_tmr_blk = pm_base + 0x8;
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fadt->gpe0_blk = pm_base + 0x20;
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 8;
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if (is_mcp55) {
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fadt->gpe1_blk = pm_base + 0x4a0;
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fadt->gpe1_base = 0x20;
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fadt->gpe1_blk_len = 0x10;
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}
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else {
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fadt->gpe1_blk = 0x0;
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fadt->gpe1_base = 0x0;
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fadt->gpe1_blk_len = 0x0;
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}
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fadt->cst_cnt = 0;
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fadt->p_lvl2_lat = 0x65;
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fadt->p_lvl3_lat = 0x3e9;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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fadt->duty_width = 3;
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fadt->day_alrm = 0x7d;
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fadt->mon_alrm = 0x7e;
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fadt->century = 0x32;
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fadt->iapc_boot_arch = 0x0;
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fadt->flags = 0x4a5;
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fadt->reset_reg.space_id = 0;
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fadt->reset_reg.bit_width = 0;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.resv = 0;
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fadt->reset_reg.addrl = 0x0;
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fadt->reset_reg.addrh = 0x0;
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fadt->reset_value = 0;
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fadt->x_firmware_ctl_l = facs;
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = dsdt;
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fadt->x_dsdt_h = 0;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.resv = 0;
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fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = 1;
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fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.resv = 0;
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fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.resv = 0;
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = 1;
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fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.resv = 0;
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fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = 1;
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fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.resv = 0;
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fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.resv = 0;
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = 1;
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.resv = 0;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0x0;
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fadt->x_gpe1_blk.space_id = 1;
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fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.resv = 0;
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fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
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fadt->x_gpe1_blk.addrh = 0x0;
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header->checksum = acpi_checksum((void *) fadt, header->length);
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}
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@@ -155,7 +155,6 @@ static void lpc_slave_init(device_t dev)
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lpc_common_init(dev, 0);
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}
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#if 0
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static void enable_hpet(struct device *dev)
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{
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unsigned long hpet_address;
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@@ -164,7 +163,6 @@ static void enable_hpet(struct device *dev)
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hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
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printk_debug("enabling HPET @0x%x\n", hpet_address);
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}
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#endif
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static void lpc_init(device_t dev)
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{
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@@ -242,7 +240,7 @@ static void lpc_init(device_t dev)
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isa_dma_init();
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/* Initialize the High Precision Event Timers */
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// enable_hpet(dev);
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enable_hpet(dev);
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}
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