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{cpu,soc}/intel: replace AES-NI locking by common implemenation call

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Deduplicate code by using the new common cpu code implementation of
AES-NI locking.

Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner
2020-10-11 17:34:54 +02:00
parent 2ac743330c
commit 63032439f4
9 changed files with 12 additions and 46 deletions
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22
src/soc/intel/skylake/cpu.c
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@@ -186,25 +186,6 @@ static void enable_pm_timer_emulation(void)
wrmsr(MSR_EMULATE_PM_TIMER, msr);
}
/*
* Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling
* as suggested in Intel document 325384-070US.
*/
static void cpu_lock_aesni(void)
{
msr_t msr;
/* Only run once per core as specified in the MSR datasheet */
if (intel_ht_sibling())
return;
msr = rdmsr(MSR_FEATURE_CONFIG);
if ((msr.lo & 1) == 0) {
msr.lo |= 1;
wrmsr(MSR_FEATURE_CONFIG, msr);
}
}
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
@@ -227,8 +208,7 @@ void soc_core_init(struct device *cpu)
/* Configure Intel Speed Shift */
configure_isst();
/* Lock AES-NI MSR */
cpu_lock_aesni();
set_aesni_lock();
/* Enable ACPI Timer Emulation via MSR 0x121 */
enable_pm_timer_emulation();