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sb/intel/*: Delete early_spi

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The file and all of it's functions are unused. Drop the dead code.

Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph
2019-05-08 18:58:55 +02:00
committed by Patrick Georgi
parent 2bb432ece6
commit 6336ee6df9
20 changed files with 2 additions and 607 deletions
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1
src/soc/intel/baytrail/include/soc/romstage.h
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@@ -37,7 +37,6 @@ void gfx_init(void);
void tco_disable(void);
void punit_init(void);
void set_max_freq(void);
int early_spi_read_wpsr(u8 *sr);
#if CONFIG(ENABLE_BUILTIN_COM1)
void byt_config_com1_and_enable(void);

1
src/soc/intel/baytrail/romstage/Makefile.inc
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@@ -5,4 +5,3 @@ romstage-y += raminit.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
romstage-y += gfx.c
romstage-y += pmc.c
romstage-y += early_spi.c

60
src/soc/intel/baytrail/romstage/early_spi.c
View File

@@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>
#include <console/console.h>
#include <soc/iomap.h>
#include <soc/romstage.h>
#include <soc/spi.h>
#define SPI_CYCLE_DELAY 10 /* 10us */
#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */
#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x))
#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x))
#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x))
/* Minimal set of commands to read wpsr from SPI. Don't use this code outside
* romstage -- it trashes the opmenu table.
* Returns 0 on success, < 0 on failure. */
int early_spi_read_wpsr(u8 *sr)
{
int timeout = SPI_CYCLE_TIMEOUT;
/* No address associated with rdsr */
SPI8(OPTYPE) = 0x0;
/* Setup opcode[0] = read wpsr */
SPI8(OPMENU0) = 0x5;
/* Start transaction */
SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO;
/* Wait for error / complete status */
while (timeout--) {
u16 status = SPI16(SSFS);
if (status & FLASH_CYCLE_ERROR) {
printk(BIOS_ERR, "SPI rdsr failed\n");
return -1;
} else if (status & CYCLE_DONE_STATUS)
break;
udelay(SPI_CYCLE_DELAY);
}
*sr = SPI32(FDATA0) & 0xff;
return 0;
}