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src/mainboard/a-trend - emulation: Add space around operators

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Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16616
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Elyes HAOUAS
2016-09-16 20:49:38 +02:00
committed by Patrick Georgi
parent ed5f159ed5
commit 6350a2e43f
85 changed files with 370 additions and 370 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/mainboard/a-trend/atc-6220/irq_tables.c
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@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x4e, /* Checksum */ 0x4e, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
{0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x07 << 3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
} }
}; };

14
src/mainboard/a-trend/atc-6240/irq_tables.c
View File

@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x44, /* Checksum */ 0x44, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0e<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0e << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0},
{0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
} }
}; };

18
src/mainboard/abit/be6-ii_v2_0/irq_tables.c
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@ -30,15 +30,15 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x4b, /* Checksum */ 0x4b, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x13<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x13 << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x11<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x11 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x61, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x0f << 3)|0x0, {{0x61, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0},
{0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x6, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x6, 0x0},
{0x00,(0x08<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x7, 0x0}, {0x00,(0x08 << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x7, 0x0},
{0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
} }
}; };

26
src/mainboard/adi/rcc-dff/irq_tables.c
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@ -33,7 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x0F1C, /* Device */ 0x0F1C, /* Device */
@ -42,18 +42,18 @@ const struct irq_routing_table intel_irq_routing_table = {
0x86, /* u8 checksum. */ 0x86, /* u8 checksum. */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
{0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
{0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
{0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
{0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
{0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
{0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
{0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
{0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
} }
}; };

2
src/mainboard/advansus/a785e-i/romstage.c
View File

@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

2
src/mainboard/amd/bimini_fam10/romstage.c
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@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

8
src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
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@ -292,10 +292,10 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
/* Azalia Controller OEM Codec Table Pointer */ /* Azalia Controller OEM Codec Table Pointer */
FchParams->Azalia.AzaliaPinCfg = TRUE; FchParams->Azalia.AzaliaPinCfg = TRUE;
FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){
.AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03, .AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03,
.AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03, .AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03,
.AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03, .AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03,
.AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03 .AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03
}; };
FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList;
/* Azalia Controller Front Panel OEM Table Pointer */ /* Azalia Controller Front Panel OEM Table Pointer */

6
src/mainboard/amd/dbm690t/fadt.c
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@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt; fadt->dsdt = (u32) dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */ /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
fadt->preferred_pm_profile = 0x03; fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9; fadt->sci_int = 9;
/* disable system management mode by setting to 0: */ /* disable system management mode by setting to 0: */
@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
* the contents of the PM registers at * the contents of the PM registers at
* index 20-2B to decode ACPI I/O address. * index 20-2B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/ * AcpiSmiEn & SmiCmdEn*/
pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;

2
src/mainboard/amd/dbm690t/mptable.c
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@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

4
src/mainboard/amd/dbm690t/romstage.c
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@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cpuid1 = cpuid(0x80000007); cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) { if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */ /* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change();
@ -117,7 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else { } else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); printk(BIOS_DEBUG, "Changing FIDVID not supported\n");

2
src/mainboard/amd/dinar/fadt.c
View File

@ -54,7 +54,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
else else
fadt->dsdt = (uintptr_t)dsdt; fadt->dsdt = (uintptr_t)dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */ /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
fadt->preferred_pm_profile = 0x03; fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9; fadt->sci_int = 9;
/* disable system management mode by setting to 0: */ /* disable system management mode by setting to 0: */

6
src/mainboard/amd/dinar/gpio.c
View File

@ -179,7 +179,7 @@ gpioEarlyInit(
RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
@ -357,7 +357,7 @@ gpioEarlyInit(
} }
// else // else
// { // 0 - AUTO // { // 0 - AUTO
// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
// } // }
@ -377,7 +377,7 @@ gpioEarlyInit(
} }
// else // else
// { // 0 - AUTO // { // 0 - AUTO
// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
// //

24
src/mainboard/amd/dinar/gpio.h
View File

@ -341,8 +341,8 @@
#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA #define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA
#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD #define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD
#define TYPE_GPI (1<<5) #define TYPE_GPI (1 << 5)
#define TYPE_GPO (0<<5) #define TYPE_GPO (0 << 5)
#define GPIO_00_TYPE TYPE_GPO #define GPIO_00_TYPE TYPE_GPO
#define GPIO_01_TYPE TYPE_GPO #define GPIO_01_TYPE TYPE_GPO
@ -578,8 +578,8 @@
#define GPIO_228_TYPE TYPE_GPO #define GPIO_228_TYPE TYPE_GPO
#define GPIO_229_TYPE TYPE_GPO #define GPIO_229_TYPE TYPE_GPO
#define GPO_LOW (0<<6) #define GPO_LOW (0 << 6)
#define GPO_HI (1<<6) #define GPO_HI (1 << 6)
#define GPO_00_LEVEL GPO_HI #define GPO_00_LEVEL GPO_HI
#define GPO_01_LEVEL GPO_HI #define GPO_01_LEVEL GPO_HI
@ -812,8 +812,8 @@
#define GPO_228_LEVEL GPO_LOW #define GPO_228_LEVEL GPO_LOW
#define GPO_229_LEVEL GPO_LOW #define GPO_229_LEVEL GPO_LOW
#define GPIO_NONSTICKY (0<<2) #define GPIO_NONSTICKY (0 << 2)
#define GPIO_STICKY (1<<2) #define GPIO_STICKY (1 << 2)
#define GPIO_00_STICKY GPIO_NONSTICKY #define GPIO_00_STICKY GPIO_NONSTICKY
#define GPIO_01_STICKY GPIO_NONSTICKY #define GPIO_01_STICKY GPIO_NONSTICKY
@ -1046,8 +1046,8 @@
#define GPIO_228_STICKY GPIO_NONSTICKY #define GPIO_228_STICKY GPIO_NONSTICKY
#define GPIO_229_STICKY GPIO_NONSTICKY #define GPIO_229_STICKY GPIO_NONSTICKY
#define PULLUP_ENABLE (0<<3) #define PULLUP_ENABLE (0 << 3)
#define PULLUP_DISABLE (1<<3) #define PULLUP_DISABLE (1 << 3)
#define GPIO_00_PULLUP PULLUP_DISABLE #define GPIO_00_PULLUP PULLUP_DISABLE
#define GPIO_01_PULLUP PULLUP_DISABLE #define GPIO_01_PULLUP PULLUP_DISABLE
@ -1282,8 +1282,8 @@
#define GPIO_228_PULLUP PULLUP_DISABLE #define GPIO_228_PULLUP PULLUP_DISABLE
#define GPIO_229_PULLUP PULLUP_DISABLE #define GPIO_229_PULLUP PULLUP_DISABLE
#define PULLDOWN_ENABLE (1<<4) #define PULLDOWN_ENABLE (1 << 4)
#define PULLDOWN_DISABLE (0<<4) #define PULLDOWN_DISABLE (0 << 4)
#define GPIO_00_PULLDOWN PULLDOWN_DISABLE #define GPIO_00_PULLDOWN PULLDOWN_DISABLE
#define GPIO_01_PULLDOWN PULLDOWN_DISABLE #define GPIO_01_PULLDOWN PULLDOWN_DISABLE
@ -1750,7 +1750,7 @@
typedef enum _GPIO_COUNT typedef enum _GPIO_COUNT
{ {
GPIO_00=0, GPIO_00 = 0,
GPIO_01, GPIO_01,
GPIO_02, GPIO_02,
GPIO_03, GPIO_03,
@ -2227,7 +2227,7 @@ GPIO_SETTINGS gpio_table[]=
typedef enum _GEVENT_COUNT typedef enum _GEVENT_COUNT
{ {
GEVENT_00=0x60, GEVENT_00 = 0x60,
GEVENT_01, GEVENT_01,
GEVENT_02, GEVENT_02,
GEVENT_03, GEVENT_03,

6
src/mainboard/amd/inagua/BiosCallOuts.c
View File

@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
/* Get SB MMIO Base (AcpiMmioAddr) */ /* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27); WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8; Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26); WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 |= Data8; Data16 |= Data8;
@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
// Get SB800 MMIO Base (AcpiMmioAddr) // Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27); WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16=Data8<<8; Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26); WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16|=Data8; Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16; AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

26
src/mainboard/amd/inagua/broadcom.c
View File

@ -73,7 +73,7 @@ void broadcom_init(void);
* programmed with register 0x5A4 of the MAC. AMD renamed them to "GBE_STAT" and * programmed with register 0x5A4 of the MAC. AMD renamed them to "GBE_STAT" and
* won't say anything about their purpose. Appearently hardware designers are * won't say anything about their purpose. Appearently hardware designers are
* expected to blindly copy the Inagua reference schematic: GBE_STAT2: * expected to blindly copy the Inagua reference schematic: GBE_STAT2:
* 0=activity; GBE_STAT[1:0]: 11=no link, 10=10Mbit, 01=100Mbit, 00=1Gbit. * 0 = activity; GBE_STAT[1:0]: 11 = no link, 10 = 10Mbit, 01 = 100Mbit, 00 = 1Gbit.
* *
* For package processing the 5785 also features a MIPS-based RISC CPU, booting * For package processing the 5785 also features a MIPS-based RISC CPU, booting
* from an internal ROM. The firmware loads config data and supplements (e.g. to * from an internal ROM. The firmware loads config data and supplements (e.g. to
@ -119,7 +119,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
u16 basic_config; //?, see below u16 basic_config; //?, see below
u8 checksum; //byte sum of header == 0 u8 checksum; //byte sum of header == 0
u8 unknown2; //?, patch rejected if changed u8 unknown2; //?, patch rejected if changed
u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1=a, 2=b, ...) u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...)
} header; } header;
struct { /* Init code */ struct { /* Init code */
@ -197,8 +197,8 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
/* Bitfield enabling general features/codepaths in the firmware or /* Bitfield enabling general features/codepaths in the firmware or
* selecting support for one of several supported PHYs? * selecting support for one of several supported PHYs?
* Bits not listed had no appearent effect: * Bits not listed had no appearent effect:
* 14-11: any bit 1=firmware execution seemed delayed * 14-11: any bit 1 = firmware execution seemed delayed
* 10: 0=firmware execution seemed delayed * 10: 0 = firmware execution seemed delayed
* 9,2,0: select PHY type, affects these registers, probably more * 9,2,0: select PHY type, affects these registers, probably more
* 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes * 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes
* -------+---------------------------------------------------------- * -------+----------------------------------------------------------
@ -221,7 +221,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
* never seen used. Generally, lower values appear to be run earlier. * never seen used. Generally, lower values appear to be run earlier.
* An "ifconfig up" with Linux' "tg3" driver causes the tags 0x50, 60, * An "ifconfig up" with Linux' "tg3" driver causes the tags 0x50, 60,
* 68, 20, 70, 80 to be interpreted in this order. * 68, 20, 70, 80 to be interpreted in this order.
* All tests were performed with .basic_config=0x0604. * All tests were performed with .basic_config = 0x0604.
*/ */
.init.hunk1_when = 0x10, //only once at RISC CPU reset? .init.hunk1_when = 0x10, //only once at RISC CPU reset?
/* Instructions are obviously a specialized bytecode interpreted by the /* Instructions are obviously a specialized bytecode interpreted by the
@ -250,7 +250,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105
be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical)
#endif #endif
be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12=1: auto-clock-switch be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12 = 1: auto-clock-switch
be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars
be(0x06100D38), be(0x00000000), //v1.03 : - | be(0x06100D38), be(0x00000000), //v1.03 : - |
be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F|
@ -287,7 +287,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
be(0x08380000), //CFR-AF: PHY18| be(0x08380000), //CFR-AF: PHY18|
be(0x083C0000), //CFR-AF: PHY1C| be(0x083C0000), //CFR-AF: PHY1C|
#endif #endif
be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0==1 -->skip next 12 bytes be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes
#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode
#else #else
@ -304,9 +304,9 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY
#endif #endif
be(0xF7F30116), // IDDQ PHY be(0xF7F30116), // IDDQ PHY
be(0xC40005A0), //v1.09 : 5A0.0=0: Port Mode = MII be(0xC40005A0), //v1.09 : 5A0.0 = 0: Port Mode = MII
be(0xC4180400), //v1.09 : 400.3=0| be(0xC4180400), //v1.09 : 400.3 = 0|
be(0xC3100400), //v1.09 : 400.2=1| be(0xC3100400), //v1.09 : 400.2 = 1|
}, //-->PWRDN_LENGTH! }, //-->PWRDN_LENGTH!
}; };
@ -326,10 +326,10 @@ void broadcom_init(void)
printk(BIOS_DEBUG, "Upload GbE 'NV'RAM contents @ 0x%08lx\n", (unsigned long)gec_shadow); printk(BIOS_DEBUG, "Upload GbE 'NV'RAM contents @ 0x%08lx\n", (unsigned long)gec_shadow);
/* Halt RISC CPU before uploading the firmware patch */ /* Halt RISC CPU before uploading the firmware patch */
for (i=10000; i > 0; i--) { for (i = 10000; i > 0; i--) {
gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state
gec_base[0x5000/4] |= (1<<10); //issue RISC halt gec_base[0x5000/4] |= (1 << 10); //issue RISC halt
if (gec_base[0x5000/4] | (1<<10)) if (gec_base[0x5000/4] | (1 << 10))
break; break;
udelay(10); udelay(10);
} }

8
src/mainboard/amd/lamar/BiosCallOuts.c
View File

@ -321,10 +321,10 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
/* Azalia Controller OEM Codec Table Pointer */ /* Azalia Controller OEM Codec Table Pointer */
FchParams->Azalia.AzaliaPinCfg = TRUE; FchParams->Azalia.AzaliaPinCfg = TRUE;
FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){
.AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03, .AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03,
.AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03, .AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03,
.AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03, .AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03,
.AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03 .AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03
}; };
FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList;
/* Azalia Controller Front Panel OEM Table Pointer */ /* Azalia Controller Front Panel OEM Table Pointer */

2
src/mainboard/amd/mahogany/mptable.c
View File

@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

4
src/mainboard/amd/mahogany/romstage.c
View File

@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cpuid1 = cpuid(0x80000007); cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) { if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */ /* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change();
@ -118,7 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else { } else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); printk(BIOS_DEBUG, "Changing FIDVID not supported\n");

2
src/mainboard/amd/mahogany_fam10/mptable.c
View File

@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

4
src/mainboard/amd/persimmon/BiosCallOuts.c
View File

@ -63,10 +63,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
// Get SB800 MMIO Base (AcpiMmioAddr) // Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27); WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16=Data8<<8; Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26); WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16|=Data8; Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16; AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

6
src/mainboard/amd/pistachio/fadt.c
View File

@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt; fadt->dsdt = (u32) dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */ /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
fadt->preferred_pm_profile = 0x03; fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9; fadt->sci_int = 9;
/* disable system management mode by setting to 0: */ /* disable system management mode by setting to 0: */
@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
* the contents of the PM registers at * the contents of the PM registers at
* index 20-2B to decode ACPI I/O address. * index 20-2B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/ * AcpiSmiEn & SmiCmdEn*/
pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;

2
src/mainboard/amd/pistachio/mptable.c
View File

@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

4
src/mainboard/amd/pistachio/romstage.c
View File

@ -112,7 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cpuid1 = cpuid(0x80000007); cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) { if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */ /* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change();
@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else { } else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); printk(BIOS_DEBUG, "Changing FIDVID not supported\n");

6
src/mainboard/amd/rumba/irq_tables.c
View File

@ -36,7 +36,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x12 << 3)|0x0, /* Where the interrupt router lies (dev) */
0x800, /* IRQs devoted exclusively to PCI usage */ 0x800, /* IRQs devoted exclusively to PCI usage */
0x1078, /* Vendor */ 0x1078, /* Vendor */
0x2, /* Device */ 0x2, /* Device */
@ -45,8 +45,8 @@ static const struct irq_routing_table intel_irq_routing_table = {
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
} }
}; };
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)

8
src/mainboard/amd/serengeti_cheetah/acpi_tables.c
View File

@ -37,7 +37,7 @@
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
u32 gsi_base=0x18; u32 gsi_base = 0x18;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
int i; int i;
int j = 0; int j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
u32 d = 0; u32 d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4 // 8131 need to use +4
@ -149,11 +149,11 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink
const char *file_name; const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue; if((sysconf.pci1234[i] & 1) != 1 ) continue;
u8 c; u8 c;
if(i<7) { if(i < 7) {
c = (u8) ('4' + i - 1); c = (u8) ('4' + i - 1);
} }
else { else {

8
src/mainboard/amd/serengeti_cheetah/fadt.c
View File

@ -37,13 +37,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id,ASLC,4); memcpy(header->asl_compiler_id,ASLC,4);
header->asl_compiler_revision=0; header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs; fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt; fadt->dsdt= (u32)dsdt;
// 3=Workstation,4=Enterprise Server, 7=Performance Server // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
fadt->preferred_pm_profile=0x03; fadt->preferred_pm_profile = 0x03;
fadt->sci_int=9; fadt->sci_int = 9;
// disable system management mode by setting to 0: // disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f; fadt->smi_cmd = 0;//pm_base+0x2f;
fadt->acpi_enable = 0xf0; fadt->acpi_enable = 0xf0;

2
src/mainboard/amd/serengeti_cheetah/irq_tables.c
View File

@ -124,7 +124,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num++; slot_num++;
//pcix bridge //pcix bridge
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++; // pirq_info++; slot_num++;
int j = 0; int j = 0;

30
src/mainboard/amd/serengeti_cheetah/mptable.c
View File

@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
j = 0; j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) { switch(sysconf.hcid[i]) {
@ -101,34 +101,34 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB // Onboard AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
//Slot 3 PCI 32 //Slot 3 PCI 32
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
} }
//Slot 4 PCI 32 //Slot 4 PCI 32
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
} }
//Slot 1 PCI-X 133/100/66 //Slot 1 PCI-X 133/100/66
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
} }
//Slot 2 PCI-X 133/100/66 //Slot 2 PCI-X 133/100/66
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
} }
j = 0; j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
int ii; int ii;
device_t dev; device_t dev;
@ -141,8 +141,8 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
//Slot 1 PCI-X 133/100/66 //Slot 1 PCI-X 133/100/66
for(ii=0;ii<4;ii++) { for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
} }
} }
} }
@ -152,8 +152,8 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
//Slot 2 PCI-X 133/100/66 //Slot 2 PCI-X 133/100/66
for(ii=0;ii<4;ii++) { for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
} }
} }
} }

24
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -38,8 +38,8 @@
static void memreset_setup(void) static void memreset_setup(void)
{ {
//GPIO on amd8111 to enable MEMRST ???? //GPIO on amd8111 to enable MEMRST ????
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
} }
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void memreset(int controllers, const struct mem_controller *ctrl) { }
@ -49,11 +49,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
#define SMBUS_HUB 0x18 #define SMBUS_HUB 0x18
int ret,i; int ret,i;
unsigned device=(ctrl->channel0[0])>>8; unsigned device=(ctrl->channel0[0])>>8;
/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
i=2; i = 2;
do { do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device); ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
} while ((ret!=0) && (i-->0)); } while ((ret != 0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0); smbus_write_byte(SMBUS_HUB, 0x03, 0);
} }
@ -74,10 +74,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
#define RC0 ((1<<0)<<8) #define RC0 ((1 << 0)<<8)
#define RC1 ((1<<1)<<8) #define RC1 ((1 << 1)<<8)
#define RC2 ((1<<2)<<8) #define RC2 ((1 << 2)<<8)
#define RC3 ((1<<3)<<8) #define RC3 ((1 << 3)<<8)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
/* Read FIDVID_STATUS */ /* Read FIDVID_STATUS */
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if 0 #if 0
int i; int i;
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
activate_spd_rom(&cpu[i]); activate_spd_rom(&cpu[i]);
dump_smbus_registers(); dump_smbus_registers();
} }

8
src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
View File

@ -29,7 +29,7 @@
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
u32 gsi_base=0x18; u32 gsi_base = 0x18;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current)
int i; int i;
int j = 0; int j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i < sysconf.hc_possible_num; i++) {
u32 d = 0; u32 d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4 // 8131 need to use +4
@ -138,11 +138,11 @@ unsigned long mainboard_write_acpi_tables(device_t device,
/* same htio, but different possition? We may have to copy, /* same htio, but different possition? We may have to copy,
change HCIN, and recalculate the checknum and add_table */ change HCIN, and recalculate the checknum and add_table */
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink
const char *file_name; const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue; if((sysconf.pci1234[i] & 1) != 1 ) continue;
u8 c; u8 c;
if(i<7) { if(i < 7) {
c = (u8) ('4' + i - 1); c = (u8) ('4' + i - 1);
} }
else { else {

8
src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
View File

@ -40,13 +40,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id,ASLC,4); memcpy(header->asl_compiler_id,ASLC,4);
header->asl_compiler_revision=0; header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs; fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt; fadt->dsdt= (u32)dsdt;
// 3=Workstation,4=Enterprise Server, 7=Performance Server // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
fadt->preferred_pm_profile=0x03; fadt->preferred_pm_profile = 0x03;
fadt->sci_int=9; fadt->sci_int = 9;
// disable system management mode by setting to 0: // disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f; fadt->smi_cmd = 0;//pm_base+0x2f;
fadt->acpi_enable = 0xf0; fadt->acpi_enable = 0xf0;

8
src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
View File

@ -103,7 +103,7 @@ void get_bus_conf(void)
m = sysconf.mb; m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) { for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i]; sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i]; sysconf.hcdn[i] = hcdnx[i];
} }
@ -141,8 +141,8 @@ void get_bus_conf(void)
} }
/* HT chain 1 */ /* HT chain 1 */
j=0; j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
// check hcid type here // check hcid type here
@ -199,7 +199,7 @@ void get_bus_conf(void)
m->apicid_8111 = apicid_base + 0; m->apicid_8111 = apicid_base + 0;
m->apicid_8132_1 = apicid_base + 1; m->apicid_8132_1 = apicid_base + 1;
m->apicid_8132_2 = apicid_base + 2; m->apicid_8132_2 = apicid_base + 2;
for(i=0;i<j;i++) { for(i = 0; i < j; i++) {
m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
} }

2
src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
View File

@ -94,7 +94,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num++; slot_num++;
//pcix bridge //pcix bridge
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++; // pirq_info++; slot_num++;
int j = 0; int j = 0;

34
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
j = 0; j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) { switch(sysconf.hcid[i]) {
@ -103,34 +103,34 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB // Onboard AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
//Slot 3 PCI 32 //Slot 3 PCI 32
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
} }
// Slot 4 PCI 32 // Slot 4 PCI 32
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
} }
// Slot 1 PCI-X 133/100/66 // Slot 1 PCI-X 133/100/66
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
} }
//Slot 2 PCI-X 133/100/66 //Slot 2 PCI-X 133/100/66
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
} }
j = 0; j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
int ii; int ii;
int jj; int jj;
@ -143,10 +143,10 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
for(jj=0; jj<4; jj++) { for(jj = 0; jj < 4; jj++) {
//Slot 1 PCI-X 133/100/66 //Slot 1 PCI-X 133/100/66
for(ii=0;ii<4;ii++) { for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
} }
} }
} }
@ -156,10 +156,10 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
for(jj=0; jj<4; jj++) { for(jj = 0; jj < 4; jj++) {
//Slot 2 PCI-X 133/100/66 //Slot 2 PCI-X 133/100/66
for(ii=0;ii<4;ii++) { for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
} }
} }
} }

12
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -51,8 +51,8 @@
static void memreset_setup(void) static void memreset_setup(void)
{ {
//GPIO on amd8111 to enable MEMRST ???? //GPIO on amd8111 to enable MEMRST ????
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1 outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN = 1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
} }
static void activate_spd_rom(const struct mem_controller *ctrl) static void activate_spd_rom(const struct mem_controller *ctrl)
@ -63,11 +63,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id); printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id);
/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
i=2; i = 2;
do { do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7))); ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7)));
} while ((ret!=0) && (i-->0)); } while ((ret != 0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0); smbus_write_byte(SMBUS_HUB, 0x03, 0);
} }
@ -277,7 +277,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

6
src/mainboard/amd/south_station/BiosCallOuts.c
View File

@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
/* Get SB MMIO Base (AcpiMmioAddr) */ /* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27); WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8; Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26); WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 |= Data8; Data16 |= Data8;
@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
// Get SB800 MMIO Base (AcpiMmioAddr) // Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27); WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16=Data8<<8; Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26); WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16|=Data8; Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16; AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

2
src/mainboard/amd/tilapia_fam10/mptable.c
View File

@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

6
src/mainboard/amd/torpedo/BiosCallOuts.c
View File

@ -58,7 +58,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
/* Get SB MMIO Base (AcpiMmioAddr) */ /* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27); WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8; Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26); WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 |= Data8; Data16 |= Data8;
@ -108,10 +108,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
// Get SB MMIO Base (AcpiMmioAddr) // Get SB MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27); WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16=Data8<<8; Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26); WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16|=Data8; Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16; AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

2
src/mainboard/amd/torpedo/fadt.c
View File

@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
else else
fadt->dsdt = (uintptr_t)dsdt; fadt->dsdt = (uintptr_t)dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */ /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
fadt->preferred_pm_profile = 0x03; fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9; fadt->sci_int = 9;
/* disable system management mode by setting to 0: */ /* disable system management mode by setting to 0: */

6
src/mainboard/amd/torpedo/gpio.c
View File

@ -177,7 +177,7 @@ gpioEarlyInit(
RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
@ -355,7 +355,7 @@ gpioEarlyInit(
} }
// else // else
// { // 0 - AUTO // { // 0 - AUTO
// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
// } // }
@ -375,7 +375,7 @@ gpioEarlyInit(
} }
// else // else
// { // 0 - AUTO // { // 0 - AUTO
// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
// //

24
src/mainboard/amd/torpedo/gpio.h
View File

@ -341,8 +341,8 @@
#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA #define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA
#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD #define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD
#define TYPE_GPI (1<<5) #define TYPE_GPI (1 << 5)
#define TYPE_GPO (0<<5) #define TYPE_GPO (0 << 5)
#define GPIO_00_TYPE TYPE_GPO #define GPIO_00_TYPE TYPE_GPO
#define GPIO_01_TYPE TYPE_GPO #define GPIO_01_TYPE TYPE_GPO
@ -578,8 +578,8 @@
#define GPIO_228_TYPE TYPE_GPO #define GPIO_228_TYPE TYPE_GPO
#define GPIO_229_TYPE TYPE_GPO #define GPIO_229_TYPE TYPE_GPO
#define GPO_LOW (0<<6) #define GPO_LOW (0 << 6)
#define GPO_HI (1<<6) #define GPO_HI (1 << 6)
#define GPO_00_LEVEL GPO_HI #define GPO_00_LEVEL GPO_HI
#define GPO_01_LEVEL GPO_HI #define GPO_01_LEVEL GPO_HI
@ -812,8 +812,8 @@
#define GPO_228_LEVEL GPO_LOW #define GPO_228_LEVEL GPO_LOW
#define GPO_229_LEVEL GPO_LOW #define GPO_229_LEVEL GPO_LOW
#define GPIO_NONSTICKY (0<<2) #define GPIO_NONSTICKY (0 << 2)
#define GPIO_STICKY (1<<2) #define GPIO_STICKY (1 << 2)
#define GPIO_00_STICKY GPIO_NONSTICKY #define GPIO_00_STICKY GPIO_NONSTICKY
#define GPIO_01_STICKY GPIO_NONSTICKY #define GPIO_01_STICKY GPIO_NONSTICKY
@ -1046,8 +1046,8 @@
#define GPIO_228_STICKY GPIO_NONSTICKY #define GPIO_228_STICKY GPIO_NONSTICKY
#define GPIO_229_STICKY GPIO_NONSTICKY #define GPIO_229_STICKY GPIO_NONSTICKY
#define PULLUP_ENABLE (0<<3) #define PULLUP_ENABLE (0 << 3)
#define PULLUP_DISABLE (1<<3) #define PULLUP_DISABLE (1 << 3)
#define GPIO_00_PULLUP PULLUP_DISABLE #define GPIO_00_PULLUP PULLUP_DISABLE
#define GPIO_01_PULLUP PULLUP_DISABLE #define GPIO_01_PULLUP PULLUP_DISABLE
@ -1282,8 +1282,8 @@
#define GPIO_228_PULLUP PULLUP_DISABLE #define GPIO_228_PULLUP PULLUP_DISABLE
#define GPIO_229_PULLUP PULLUP_DISABLE #define GPIO_229_PULLUP PULLUP_DISABLE
#define PULLDOWN_ENABLE (1<<4) #define PULLDOWN_ENABLE (1 << 4)
#define PULLDOWN_DISABLE (0<<4) #define PULLDOWN_DISABLE (0 << 4)
#define GPIO_00_PULLDOWN PULLDOWN_DISABLE #define GPIO_00_PULLDOWN PULLDOWN_DISABLE
#define GPIO_01_PULLDOWN PULLDOWN_DISABLE #define GPIO_01_PULLDOWN PULLDOWN_DISABLE
@ -1750,7 +1750,7 @@
typedef enum _GPIO_COUNT typedef enum _GPIO_COUNT
{ {
GPIO_00=0, GPIO_00 = 0,
GPIO_01, GPIO_01,
GPIO_02, GPIO_02,
GPIO_03, GPIO_03,
@ -2227,7 +2227,7 @@ const GPIO_SETTINGS gpio_table[]=
typedef enum _GEVENT_COUNT typedef enum _GEVENT_COUNT
{ {
GEVENT_00=0x60, GEVENT_00 = 0x60,
GEVENT_01, GEVENT_01,
GEVENT_02, GEVENT_02,
GEVENT_03, GEVENT_03,

6
src/mainboard/amd/union_station/BiosCallOuts.c
View File

@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
/* Get SB MMIO Base (AcpiMmioAddr) */ /* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27); WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8; Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26); WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 |= Data8; Data16 |= Data8;
@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
// Get SB800 MMIO Base (AcpiMmioAddr) // Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27); WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16=Data8<<8; Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26); WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16|=Data8; Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16; AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

2
src/mainboard/artecgroup/dbe61/romstage.c
View File

@ -36,7 +36,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
int i; int i;
if (device == DIMM0) { if (device == DIMM0) {
for (i=0; i < (ARRAY_SIZE(spd_table)); i++) { for (i = 0; i < (ARRAY_SIZE(spd_table)); i++) {
if (spd_table[i].address == address) { if (spd_table[i].address == address) {
return spd_table[i].data; return spd_table[i].data;
} }

2
src/mainboard/asrock/939a785gmh/mptable.c
View File

@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

4
src/mainboard/asrock/939a785gmh/romstage.c
View File

@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cpuid1 = cpuid(0x80000007); cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) { if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */ /* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change();
@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else { } else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); printk(BIOS_DEBUG, "Changing FIDVID not supported\n");

2
src/mainboard/asrock/e350m1/BiosCallOuts.c
View File

@ -55,7 +55,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
/* Get SB800 MMIO Base (AcpiMmioAddr) */ /* Get SB800 MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27); WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8; Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26); WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 |= Data8; Data16 |= Data8;

4
src/mainboard/asus/a8v-e_deluxe/romstage.c
View File

@ -126,8 +126,8 @@ static void sio_init(void)
pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */
pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */
pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
pnp_exit_ext_func_mode(GPIO_DEV); pnp_exit_ext_func_mode(GPIO_DEV);

4
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -126,8 +126,8 @@ static void sio_init(void)
pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */
pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */
pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
pnp_exit_ext_func_mode(GPIO_DEV); pnp_exit_ext_func_mode(GPIO_DEV);

4
src/mainboard/asus/k8v-x/mainboard.c
View File

@ -42,9 +42,9 @@ u32 vt8237_ide_80pin_detect(struct device *dev)
gpio_in = inl(acpi_io_base + 0x48); gpio_in = inl(acpi_io_base + 0x48);
/* bit 29 for primary port, clear if unconnected or 80-pin cable */ /* bit 29 for primary port, clear if unconnected or 80-pin cable */
res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; res = gpio_in & (1 << 29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
/* bit 8 for secondary port, clear if unconnected or 80-pin cable */ /* bit 8 for secondary port, clear if unconnected or 80-pin cable */
res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; res |= gpio_in & (1 << 8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);

2
src/mainboard/asus/kcma-d8/acpi_tables.c
View File

@ -30,7 +30,7 @@ unsigned long acpi_fill_madt(unsigned long current)
{ {
device_t dev; device_t dev;
u32 dword; u32 dword;
u32 gsi_base=0; u32 gsi_base = 0;
uint32_t apicid_sp5100; uint32_t apicid_sp5100;
uint32_t apicid_sr5650; uint32_t apicid_sr5650;
/* create all subtables for processors */ /* create all subtables for processors */

2
src/mainboard/asus/kcma-d8/irq_tables.c
View File

@ -24,7 +24,7 @@
#include <cpu/amd/amdfam10_sysconf.h> #include <cpu/amd/amdfam10_sysconf.h>
/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ /* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */
#define IRQBM ((1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15)) #define IRQBM ((1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 12)|(1 << 14)|(1 << 15))
#define LNKA 1 #define LNKA 1
#define LNKB 2 #define LNKB 2

2
src/mainboard/asus/kcma-d8/mptable.c
View File

@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
/* Hide IDE */ /* Hide IDE */
dword &= ~(0x00080000); dword &= ~(0x00080000);
/* dword_ptr |= 1<<22; PIC and APIC co exists */ /* dword_ptr |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

10
src/mainboard/asus/kcma-d8/romstage.c
View File

@ -256,7 +256,7 @@ static void execute_memory_test(void)
uint32_t readback; uint32_t readback;
uint32_t start = 0x300000; uint32_t start = 0x300000;
printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n");
for (i=0; i < 0x1000000; i = i + 8) { for (i = 0; i < 0x1000000; i = i + 8) {
dataptr = (void *)(start + i); dataptr = (void *)(start + i);
*dataptr = 0x55555555; *dataptr = 0x55555555;
dataptr = (void *)(start + i + 4); dataptr = (void *)(start + i + 4);
@ -264,7 +264,7 @@ static void execute_memory_test(void)
} }
printk(BIOS_DEBUG, "Done!\n"); printk(BIOS_DEBUG, "Done!\n");
printk(BIOS_DEBUG, "Testing memory...\n"); printk(BIOS_DEBUG, "Testing memory...\n");
for (i=0; i < 0x1000000; i = i + 8) { for (i = 0; i < 0x1000000; i = i + 8) {
dataptr = (void *)(start + i); dataptr = (void *)(start + i);
readback = *dataptr; readback = *dataptr;
if (readback != 0x55555555) if (readback != 0x55555555)
@ -281,7 +281,7 @@ static void execute_memory_test(void)
x = 0xaaaaaaaa; x = 0xaaaaaaaa;
y = 0x12345678; y = 0x12345678;
z = 0x87654321; z = 0x87654321;
for (i=0; i < 0x1000000; i = i + 4) { for (i = 0; i < 0x1000000; i = i + 4) {
/* Use Xorshift as a PRNG to stress test the bus */ /* Use Xorshift as a PRNG to stress test the bus */
v = x; v = x;
v ^= v << 11; v ^= v << 11;
@ -301,7 +301,7 @@ static void execute_memory_test(void)
x = 0xaaaaaaaa; x = 0xaaaaaaaa;
y = 0x12345678; y = 0x12345678;
z = 0x87654321; z = 0x87654321;
for (i=0; i < 0x1000000; i = i + 4) { for (i = 0; i < 0x1000000; i = i + 4) {
/* Use Xorshift as a PRNG to stress test the bus */ /* Use Xorshift as a PRNG to stress test the bus */
v = x; v = x;
v ^= v << 11; v ^= v << 11;
@ -499,7 +499,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
} }

2
src/mainboard/asus/kfsn4-dre/romstage.c
View File

@ -277,7 +277,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
} }

2
src/mainboard/asus/kgpe-d16/acpi_tables.c
View File

@ -30,7 +30,7 @@ unsigned long acpi_fill_madt(unsigned long current)
{ {
device_t dev; device_t dev;
u32 dword; u32 dword;
u32 gsi_base=0; u32 gsi_base = 0;
uint32_t apicid_sp5100; uint32_t apicid_sp5100;
uint32_t apicid_sr5650; uint32_t apicid_sr5650;
/* create all subtables for processors */ /* create all subtables for processors */

2
src/mainboard/asus/kgpe-d16/irq_tables.c
View File

@ -24,7 +24,7 @@
#include <cpu/amd/amdfam10_sysconf.h> #include <cpu/amd/amdfam10_sysconf.h>
/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ /* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */
#define IRQBM ((1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15)) #define IRQBM ((1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 12)|(1 << 14)|(1 << 15))
#define LNKA 1 #define LNKA 1
#define LNKB 2 #define LNKB 2

2
src/mainboard/asus/kgpe-d16/mptable.c
View File

@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
/* Hide IDE */ /* Hide IDE */
dword &= ~(0x00080000); dword &= ~(0x00080000);
/* dword_ptr |= 1<<22; PIC and APIC co exists */ /* dword_ptr |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

10
src/mainboard/asus/kgpe-d16/romstage.c
View File

@ -297,7 +297,7 @@ static void execute_memory_test(void)
uint32_t readback; uint32_t readback;
uint32_t start = 0x300000; uint32_t start = 0x300000;
printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n");
for (i=0; i < 0x1000000; i = i + 8) { for (i = 0; i < 0x1000000; i = i + 8) {
dataptr = (void *)(start + i); dataptr = (void *)(start + i);
*dataptr = 0x55555555; *dataptr = 0x55555555;
dataptr = (void *)(start + i + 4); dataptr = (void *)(start + i + 4);
@ -305,7 +305,7 @@ static void execute_memory_test(void)
} }
printk(BIOS_DEBUG, "Done!\n"); printk(BIOS_DEBUG, "Done!\n");
printk(BIOS_DEBUG, "Testing memory...\n"); printk(BIOS_DEBUG, "Testing memory...\n");
for (i=0; i < 0x1000000; i = i + 8) { for (i = 0; i < 0x1000000; i = i + 8) {
dataptr = (void *)(start + i); dataptr = (void *)(start + i);
readback = *dataptr; readback = *dataptr;
if (readback != 0x55555555) if (readback != 0x55555555)
@ -322,7 +322,7 @@ static void execute_memory_test(void)
x = 0xaaaaaaaa; x = 0xaaaaaaaa;
y = 0x12345678; y = 0x12345678;
z = 0x87654321; z = 0x87654321;
for (i=0; i < 0x1000000; i = i + 4) { for (i = 0; i < 0x1000000; i = i + 4) {
/* Use Xorshift as a PRNG to stress test the bus */ /* Use Xorshift as a PRNG to stress test the bus */
v = x; v = x;
v ^= v << 11; v ^= v << 11;
@ -342,7 +342,7 @@ static void execute_memory_test(void)
x = 0xaaaaaaaa; x = 0xaaaaaaaa;
y = 0x12345678; y = 0x12345678;
z = 0x87654321; z = 0x87654321;
for (i=0; i < 0x1000000; i = i + 4) { for (i = 0; i < 0x1000000; i = i + 4) {
/* Use Xorshift as a PRNG to stress test the bus */ /* Use Xorshift as a PRNG to stress test the bus */
v = x; v = x;
v ^= v << 11; v ^= v << 11;
@ -540,7 +540,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
} }

4
src/mainboard/asus/m2v/irq_tables.c
View File

@ -22,7 +22,7 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
/* Free irqs are 3, 5, 10 and 11 */ /* Free irqs are 3, 5, 10 and 11 */
#define IRQBM ((1<<3)|(1<<5)|(1<<10)|(1<<11)) #define IRQBM ((1 << 3)|(1 << 5)|(1 << 10)|(1 << 11))
#define LNKA 1 #define LNKA 1
#define LNKB 2 #define LNKB 2
@ -44,7 +44,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0, /* Where the interrupt router lies (bus) */ 0, /* Where the interrupt router lies (bus) */
(0x11<<3)|0, /* Where the interrupt router lies (dev) */ (0x11 << 3)|0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
PCI_VENDOR_ID_VIA, /* Compatible Vendor (VIA) */ PCI_VENDOR_ID_VIA, /* Compatible Vendor (VIA) */
PCI_DEVICE_ID_VIA_82C596, /* Compatible Device (82C596) */ PCI_DEVICE_ID_VIA_82C596, /* Compatible Device (82C596) */

4
src/mainboard/asus/m2v/mainboard.c
View File

@ -38,9 +38,9 @@ u32 vt8237_ide_80pin_detect(struct device *dev)
gpio_in = inl(acpi_io_base + 0x48); gpio_in = inl(acpi_io_base + 0x48);
/* bit 9 for primary port, clear if unconnected or 80-pin cable */ /* bit 9 for primary port, clear if unconnected or 80-pin cable */
res = gpio_in & (1<<9) ? 0 : VT8237R_IDE0_80PIN_CABLE; res = gpio_in & (1 << 9) ? 0 : VT8237R_IDE0_80PIN_CABLE;
/* bit 4 for secondary port, clear if unconnected or 80-pin cable */ /* bit 4 for secondary port, clear if unconnected or 80-pin cable */
res |= gpio_in & (1<<4) ? 0 : VT8237R_IDE1_80PIN_CABLE; res |= gpio_in & (1 << 4) ? 0 : VT8237R_IDE1_80PIN_CABLE;
printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);

8
src/mainboard/asus/m2v/romstage.c
View File

@ -154,10 +154,10 @@ static void m2v_it8712f_gpio_init(void)
* pcirst5# -> maybe n/c (untested) * pcirst5# -> maybe n/c (untested)
* *
* For software control of PCIRST[1-5]#: * For software control of PCIRST[1-5]#:
* 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control) * 0x2a = 0x17 (deselect pcirst# hardwiring, enable 0x25 control)
* 0x25=0x17 (select gpio function) * 0x25 = 0x17 (select gpio function)
* 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable * 0xc0 = 0x17, 0xc8 = 0x17 gpio port 1 select & output enable
* 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable * 0xc4 = 0xc1, 0xcc = 0xc1 gpio port 5 select & output enable
*/ */
giv = gpio_init_data; giv = gpio_init_data;
while (giv->addr) { while (giv->addr) {

2
src/mainboard/asus/m4a78-em/mptable.c
View File

@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

2
src/mainboard/asus/m4a785-m/mptable.c
View File

@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

2
src/mainboard/asus/m5a88-v/romstage.c
View File

@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

16
src/mainboard/asus/mew-am/irq_tables.c
View File

@ -30,14 +30,14 @@ static const struct irq_routing_table intel_irq_routing_table = {
0xe3, /* Checksum */ 0xe3, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x1e<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x1e << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
{0x01,(0x08<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, {0x01,(0x08 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
{0x01,(0x09<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, {0x01,(0x09 << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
{0x01,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, {0x01,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
{0x01,(0x0b<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, {0x01,(0x0b << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
{0x00,(0x1f<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x1f << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
{0x01,(0x02<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x0, 0x0}, {0x01,(0x02 << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x0, 0x0},
} }
}; };

24
src/mainboard/asus/mew-vm/irq_tables.c
View File

@ -5,7 +5,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x11 << 3)|0x0, /* Where the interrupt router lies (dev) */
0xe20, /* IRQs devoted exclusively to PCI usage */ 0xe20, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x7120, /* Device */ 0x7120, /* Device */
@ -15,17 +15,17 @@ static const struct irq_routing_table intel_irq_routing_table = {
that would give 0 after the sum of all bytes for this structure (including checksum) */ that would give 0 after the sum of all bytes for this structure (including checksum) */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08<<3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0}, {0x00,(0x08 << 3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0},
{0x00,(0x09<<3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0},
{0x00,(0x0c<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0},
{0x00,(0x11<<3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, {0x00,(0x11 << 3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, {0x00,(0x0f << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
{0x00,(0x10<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, {0x00,(0x10 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
{0x00,(0x12<<3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0}, {0x00,(0x12 << 3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0},
} }
}; };

14
src/mainboard/asus/p2b-f/irq_tables.c
View File

@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
0xf9, /* Checksum */ 0xf9, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
{0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
{0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
} }
}; };

12
src/mainboard/asus/p2b/irq_tables.c
View File

@ -30,12 +30,12 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x54, /* Checksum */ 0x54, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
{0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
{0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
} }
}; };

16
src/mainboard/asus/p3b-f/irq_tables.c
View File

@ -30,14 +30,14 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x95, /* Checksum */ 0x95, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
{0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
{0x00,(0x0e<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0}, {0x00,(0x0e << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0},
{0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
} }
}; };

2
src/mainboard/avalue/eax-785e/romstage.c
View File

@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

14
src/mainboard/azza/pt-6ibd/irq_tables.c
View File

@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x3c, /* Checksum */ 0x3c, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x09<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x0f << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
{0x00,(0x11<<3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, {0x00,(0x11 << 3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0},
{0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
} }
}; };

20
src/mainboard/bcom/winnetp680/irq_tables.c
View File

@ -31,16 +31,16 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x3e, /* Checksum */ 0x3e, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
{0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
{0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
{0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
} }
}; };

4
src/mainboard/bcom/winnetp680/romstage.c
View File

@ -48,7 +48,7 @@ static void enable_mainboard_devices(void)
if (dev == PCI_DEV_INVALID) if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n"); die("Southbridge not found!!!\n");
/* bit=0 means enable function (per CX700 datasheet) /* bit = 0 means enable function (per CX700 datasheet)
* 5 16.1 USB 2 * 5 16.1 USB 2
* 4 16.0 USB 1 * 4 16.0 USB 1
* 3 15.0 SATA and PATA * 3 15.0 SATA and PATA
@ -57,7 +57,7 @@ static void enable_mainboard_devices(void)
*/ */
pci_write_config8(dev, 0x50, 0x80); pci_write_config8(dev, 0x50, 0x80);
/* bit=1 means enable internal function (per CX700 datasheet) /* bit = 1 means enable internal function (per CX700 datasheet)
* 3 Internal RTC * 3 Internal RTC
* 2 Internal PS2 Mouse * 2 Internal PS2 Mouse
* 1 Internal KBC Configuration * 1 Internal KBC Configuration

14
src/mainboard/biostar/m6tba/irq_tables.c
View File

@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
0xc7, /* Checksum */ 0xc7, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x08 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
{0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
} }
}; };

42
src/mainboard/broadcom/blast/mptable.c
View File

@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
{ {
device_t dev = 0; device_t dev = 0;
struct resource *res; struct resource *res;
for(i=0; i<3; i++) { for(i = 0; i < 3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev); dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -59,11 +59,11 @@ static void *smp_write_config_table(void *v)
//SATA //SATA
outb(0x07, 0xc00); outb(0x0f, 0xc01); outb(0x07, 0xc00); outb(0x0f, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e << 2)|0, apicid_bcm5785[0], 0xf);
//USB //USB
outb(0x01, 0xc00); outb(0x0a, 0xc01); outb(0x01, 0xc00); outb(0x0a, 0xc01);
for(i=0;i<3;i++) { for(i = 0; i < 3; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
} }
@ -77,7 +77,7 @@ static void *smp_write_config_table(void *v)
if(dev) { if(dev) {
uint32_t dword; uint32_t dword;
dword = pci_read_config32(dev, 0x6c); dword = pci_read_config32(dev, 0x6c);
dword |= (1<<4); // enable interrupts dword |= (1 << 4); // enable interrupts
pci_write_config32(dev, 0x6c, dword); pci_write_config32(dev, 0x6c, dword);
} }
@ -85,50 +85,50 @@ static void *smp_write_config_table(void *v)
} }
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4 << 2)|i, apicid_bcm5785[1], 2 + (0+i)%4); //
} }
//pci slot (on bcm5785) //pci slot (on bcm5785)
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4 << 2)|i, apicid_bcm5785[1], i%2); //
} }
//onboard ati //onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5 << 2)|0, apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780 //PCI-X on bcm5780
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4 << 2)|i, apicid_bcm5785[1], 6 + (0+i)%4); //
} }
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5 << 2)|i, apicid_bcm5785[1], 6 + (1+i)%4); //
} }
//onboard Broadcom //onboard Broadcom
for(i=0;i<2;i++) { for(i = 0; i < 2; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4 << 2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); //
} }
// First PCI-E x8 // First PCI-E x8
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0 << 2)|i, apicid_bcm5785[1], 0xe); //
} }
// Second PCI-E x8 // Second PCI-E x8
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0 << 2)|i, apicid_bcm5785[1], 0xc); //
} }
// Third PCI-E x1 // Third PCI-E x1
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0 << 2)|i, apicid_bcm5785[1], 0xd); //
} }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/

4
src/mainboard/broadcom/blast/romstage.c
View File

@ -46,8 +46,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
#define RC0 (6<<8) #define RC0 (6 << 8)
#define RC1 (7<<8) #define RC1 (7 << 8)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

10
src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c
View File

@ -30,11 +30,11 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x97, /* Checksum */ 0x97, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0d<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0},
{0x00,(0x0e<<3)|0x0, {{0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x00ef8}}, 0x2, 0x0}, {0x00,(0x0e << 3)|0x0, {{0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x00ef8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x63, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x63, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x14<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x00ef8}}, 0x0, 0x0}, {0x00,(0x14 << 3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x00ef8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x62, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x62, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
} }
}; };

20
src/mainboard/digitallogic/msm800sev/irq_tables.c
View File

@ -42,7 +42,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x0f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x100b, /* Vendor */ 0x100b, /* Vendor */
0x2b, /* Device */ 0x2b, /* Device */
@ -53,15 +53,15 @@ static const struct irq_routing_table intel_irq_routing_table = {
bytes for this structure (including checksum) */ bytes for this structure (including checksum) */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0}, {0x00,(0x0f << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0},
{0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x13 << 3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x12 << 3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x11 << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
{0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
{0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0}, {0x00,(0x0d << 3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
} }
}; };

2
src/mainboard/emulation/qemu-armv7/Kconfig
View File

@ -16,7 +16,7 @@
# http://www.arm.com/products/tools/development-boards/versatile-express # http://www.arm.com/products/tools/development-boards/versatile-express
# To execute, do: # To execute, do:
# export QEMU_AUDIO_DRV=none # export QEMU_AUDIO_DRV = none
# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -bios build/coreboot.rom # qemu-system-arm -M vexpress-a9 -m 1024M -nographic -bios build/coreboot.rom
if BOARD_EMULATION_QEMU_ARMV7 if BOARD_EMULATION_QEMU_ARMV7

14
src/mainboard/emulation/qemu-i440fx/irq_tables.c
View File

@ -5,7 +5,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x01<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x01 << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x7000, /* Device */ 0x7000, /* Device */
@ -14,12 +14,12 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x7, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ 0x7, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
{0x00,(0x02<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, {0x00,(0x02 << 3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0},
{0x00,(0x03<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, {0x00,(0x03 << 3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
{0x00,(0x04<<3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0}, {0x00,(0x04 << 3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0},
{0x00,(0x05<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0}, {0x00,(0x05 << 3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0},
{0x00,(0x06<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0}, {0x00,(0x06 << 3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
} }
}; };
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)

2
src/mainboard/emulation/qemu-i440fx/mainboard.c
View File

@ -33,7 +33,7 @@ static void qemu_nb_init(device_t dev)
uint8_t v = pci_read_config8(dev, 0x59); uint8_t v = pci_read_config8(dev, 0x59);
v |= 0x30; v |= 0x30;
pci_write_config8(dev, 0x59, v); pci_write_config8(dev, 0x59, v);
for (i=0; i<6; i++) for (i = 0; i < 6; i++)
pci_write_config8(dev, 0x5a + i, 0x33); pci_write_config8(dev, 0x5a + i, 0x33);
/* This sneaked in here, because Qemu does not /* This sneaked in here, because Qemu does not