sb/intel/common: Create a common PCH finalise implementation

The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.

Lynx Point now benefits from being able to write-protect the flash chip.

For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.

Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.

Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.

Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/southbridge/intel/ibexpeak/Kconfig

@@ -28,6 +28,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select SOUTHBRIDGE_INTEL_COMMON
+	select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI

src/southbridge/intel/ibexpeak/Makefile.inc

@@ -37,7 +37,7 @@ ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
 ramstage-y += madt.c
 
 ramstage-y += smi.c
-smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c
+smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c
 
 romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c
 romstage-y += ../bd82x6x/early_rcba.c

src/southbridge/intel/ibexpeak/pch.h

@@ -51,10 +51,6 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
-#if defined(__SMM__) && !defined(__ASSEMBLER__)
-void intel_pch_finalize_smm(void);
-#endif
-
 #if !defined(__ASSEMBLER__)
 #if !defined(__PRE_RAM__)
 #if !defined(__SIMPLE_DEVICE__)