soc/amd/sabrina: Enable HW Modexp engine

HW Modexp engine is verified to be working fine. Any verification
failures during PSP verstage are because the firmware body is not read
correctly. This might be because of the incorrect SPI ROM mapping. Hence
enable the HW modexp engine for keyblock, preamble and firmware body
verification.

BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using one of the
FW slots.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8f6742630a7049354a24053fce28c477e53259e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/sabrina/Kconfig

@@ -45,6 +45,7 @@ config SOC_SPECIFIC_OPTIONS
 	select PLATFORM_USES_FSP2_0
 	select PROVIDES_ROM_SHARING
 	select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK
+	# TODO: b/240175446 - Enable PSP DMA after verification
 	select RESET_VECTOR_IN_RAM
 	select RTC
 	select SOC_AMD_COMMON

src/soc/amd/sabrina/psp_verstage/svc.c

@@ -174,8 +174,13 @@ uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode
 
 uint32_t svc_modexp(struct mod_exp_params *mod_exp_param)
 {
-	/* TODO: b/240175446 Re-enable CCP DMA and svc_modexp later. */
-	return 1;
+	uint32_t retval = 0;
+	struct cmd_param_modexp param = {
+		.ptr_modexp = mod_exp_param,
+	};
+	SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MODEXP, (void *)&param, retval);
+	return retval;
+
 }
 
 uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size)