sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"

Browse Source 
Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17192
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
2016-10-30 18:39:53 +01:00
committed by Martin Roth
parent 4291e8b6ca
commit 6372a0eef1
1 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/northbridge/intel/i945/early_init.c
View File

@@ -90,9 +90,9 @@ static void i945m_detect_chipset(void)
printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
} }
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC))
#endif printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
} }
static void i945_detect_chipset(void) static void i945_detect_chipset(void)
@@ -139,9 +139,9 @@ static void i945_detect_chipset(void)
printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
} }
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
#endif printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
} }
static void i945_setup_bars(void) static void i945_setup_bars(void)