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soc/intel/denverton_ns: Fix missing tsc_freq_mhz()

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It was relying on bad weak implementation for postcar
and verstage.

Change-Id: I5a520e0166198c0565349c164f143f4a43649861
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
This commit is contained in:
Kyösti Mälkki
2019-01-09 06:37:24 +02:00
parent f5a57a883b
commit 6390c50703
1 changed files with 2 additions and 0 deletions
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2
src/soc/intel/denverton_ns/Makefile.inc
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@ -31,6 +31,7 @@ bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
postcar-y += memmap.c postcar-y += memmap.c
postcar-y += spi.c postcar-y += spi.c
postcar-y += tsc_freq.c
postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
romstage-y += memmap.c romstage-y += memmap.c
@ -80,6 +81,7 @@ smm-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
verstage-y += memmap.c verstage-y += memmap.c
verstage-y += reset.c verstage-y += reset.c
verstage-y += spi.c verstage-y += spi.c
verstage-y += tsc_freq.c
verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include