ipq8064: prepare UART driver for use in coreboot
These driver needs to be in src/lib, and the include file needs to be renamed to avoid collision with the top level uart.h. BUG=chrome-os-partner:27784 TEST=emerge-storm coreboot still works Original-Change-Id: Ie12f44e055bbef0eb8b1a3ffc8d6742e7a446942 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196393 (cherry picked from commit c5618fd418642f5b009582f5f6bc51f7c9d54bec) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e25ae350ac5e71b47a0daef078b03cc5ac35401 Reviewed-on: http://review.coreboot.org/7270 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
committed by
Marc Jones
parent
30eda3edd7
commit
63956e63ce
@ -1,440 +0,0 @@
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/*
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* Copyright (c) 2012 The Linux Foundation. All rights reserved.
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* Source : APQ8064 LK boot
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*
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* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <common.h>
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#include <asm/arch-ipq806x/gsbi.h>
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#include <asm/arch-ipq806x/clock.h>
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#include <asm/arch-ipq806x/uart.h>
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#include <serial.h>
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#define FIFO_DATA_SIZE 4
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extern board_ipq806x_params_t *gboard_param;
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static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base);
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/* Received data is valid or not */
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static int valid_data = 0;
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/* Received data */
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static unsigned int word = 0;
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/**
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* msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
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* @uart_dm_base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base)
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{
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/* Reset receiver */
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writel(MSM_BOOT_UART_DM_CMD_RESET_RX,
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MSM_BOOT_UART_DM_CR(uart_dm_base));
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/* Enable receiver */
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writel(MSM_BOOT_UART_DM_CR_RX_ENABLE,
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MSM_BOOT_UART_DM_CR(uart_dm_base));
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writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE,
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MSM_BOOT_UART_DM_DMRX(uart_dm_base));
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/* Clear stale event */
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writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT,
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MSM_BOOT_UART_DM_CR(uart_dm_base));
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/* Enable stale event */
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writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT,
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MSM_BOOT_UART_DM_CR(uart_dm_base));
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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/**
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* msm_boot_uart_dm_read - reads a word from the RX FIFO.
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* @data: location where the read data is stored
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* @count: no of valid data in the FIFO
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* @wait: indicates blocking call or not blocking call
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*
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* Reads a word from the RX FIFO. If no data is available blocks if
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* @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY.
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*/
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static unsigned int
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msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
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{
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static int total_rx_data = 0;
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static int rx_data_read = 0;
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unsigned int base = 0;
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uint32_t status_reg;
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base = gboard_param->uart_dm_base;
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if (data == NULL)
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return MSM_BOOT_UART_DM_E_INVAL;
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status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
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/* Check for DM_RXSTALE for RX transfer to finish */
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while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) {
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status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
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if (!wait)
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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}
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/* Check for Overrun error. We'll just reset Error Status */
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if (readl(MSM_BOOT_UART_DM_SR(base)) &
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MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
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writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
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MSM_BOOT_UART_DM_CR(base));
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total_rx_data = rx_data_read = 0;
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msm_boot_uart_dm_init(base);
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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}
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/* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
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if (total_rx_data == 0)
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total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
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/* Data available in FIFO; read a word. */
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*data = readl(MSM_BOOT_UART_DM_RF(base, 0));
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/* WAR for http://prism/CR/548280 */
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if (*data == 0) {
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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}
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/* increment the total count of chars we've read so far */
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rx_data_read += FIFO_DATA_SIZE;
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/* actual count of valid data in word */
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*count = ((total_rx_data < rx_data_read) ?
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(FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
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FIFO_DATA_SIZE);
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/* If there are still data left in FIFO we'll read them before
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* initializing RX Transfer again
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*/
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if (rx_data_read < total_rx_data)
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return MSM_BOOT_UART_DM_E_SUCCESS;
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msm_boot_uart_dm_init_rx_transfer(base);
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total_rx_data = rx_data_read = 0;
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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/**
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* msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n"
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* @data_in: characters to be converted
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* @num_of_chars: no. of characters
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* @data_out: location where converted chars are stored
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*
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* Replace linefeed char "\n" with carriage return + linefeed
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* "\r\n". Currently keeping it simple than efficient.
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*/
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static unsigned int
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msm_boot_uart_replace_lr_with_cr(char *data_in,
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int num_of_chars,
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char *data_out, int *num_of_chars_out)
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{
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int i = 0, j = 0;
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if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0))
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return MSM_BOOT_UART_DM_E_INVAL;
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for (i = 0, j = 0; i < num_of_chars; i++, j++) {
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if (data_in[i] == '\n')
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data_out[j++] = '\r';
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data_out[j] = data_in[i];
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}
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*num_of_chars_out = j;
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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/**
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* msm_boot_uart_dm_write - transmit data
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* @data: data to transmit
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* @num_of_chars: no. of bytes to transmit
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*
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* Writes the data to the TX FIFO. If no space is available blocks
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* till space becomes available.
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*/
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static unsigned int
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msm_boot_uart_dm_write(char *data, unsigned int num_of_chars)
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{
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unsigned int tx_word_count = 0;
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unsigned int tx_char_left = 0, tx_char = 0;
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unsigned int tx_word = 0;
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int i = 0;
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char *tx_data = NULL;
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char new_data[1024];
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unsigned int base = gboard_param->uart_dm_base;
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if ((data == NULL) || (num_of_chars <= 0))
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return MSM_BOOT_UART_DM_E_INVAL;
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/* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */
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msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i);
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tx_data = new_data;
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num_of_chars = i;
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/* Write to NO_CHARS_FOR_TX register number of characters
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* to be transmitted. However, before writing TX_FIFO must
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* be empty as indicated by TX_READY interrupt in IMR register
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*/
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/* Check if transmit FIFO is empty.
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* If not we'll wait for TX_READY interrupt. */
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if (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) {
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while (!(readl(MSM_BOOT_UART_DM_ISR(base)) & MSM_BOOT_UART_DM_TX_READY))
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__udelay(1);
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}
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/* We are here. FIFO is ready to be written. */
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/* Write number of characters to be written */
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writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
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/* Clear TX_READY interrupt */
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writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(base));
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/* We use four-character word FIFO. So we need to divide data into
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* four characters and write in UART_DM_TF register */
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tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) :
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(num_of_chars / 4);
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tx_char_left = num_of_chars;
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for (i = 0; i < (int)tx_word_count; i++) {
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tx_char = (tx_char_left < 4) ? tx_char_left : 4;
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PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word);
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/* Wait till TX FIFO has space */
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while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY))
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__udelay(1);
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/* TX FIFO has space. Write the chars */
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writel(tx_word, MSM_BOOT_UART_DM_TF(base, 0));
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tx_char_left = num_of_chars - (i + 1) * 4;
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tx_data = tx_data + 4;
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}
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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/*
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* msm_boot_uart_dm_reset - resets UART controller
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* @base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_reset(unsigned int base)
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{
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writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base));
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writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base));
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writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base));
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writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base));
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writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base));
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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/*
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* msm_boot_uart_dm_init - initilaizes UART controller
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* @uart_dm_base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base)
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{
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/* Configure UART mode registers MR1 and MR2 */
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/* Hardware flow control isn't supported */
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writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base));
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/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
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writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(uart_dm_base));
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/* Configure Interrupt Mask register IMR */
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writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(uart_dm_base));
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/*
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* Configure Tx and Rx watermarks configuration registers
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* TX watermark value is set to 0 - interrupt is generated when
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* FIFO level is less than or equal to 0
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*/
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writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(uart_dm_base));
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/* RX watermark value */
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writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(uart_dm_base));
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/* Configure Interrupt Programming Register */
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/* Set initial Stale timeout value */
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writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB,
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MSM_BOOT_UART_DM_IPR(uart_dm_base));
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/* Configure IRDA if required */
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/* Disabling IRDA mode */
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writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base));
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/* Configure hunt character value in HCR register */
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/* Keep it in reset state */
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writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base));
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/*
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* Configure Rx FIFO base address
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* Both TX/RX shares same SRAM and default is half-n-half.
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* Sticking with default value now.
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* As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
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* We have found RAM_ADDR_WIDTH = 0x7f
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*/
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/* Issue soft reset command */
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msm_boot_uart_dm_reset(uart_dm_base);
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/* Enable/Disable Rx/Tx DM interfaces */
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/* Data Mover not currently utilized. */
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writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base));
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/* Enable transmitter */
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writel(MSM_BOOT_UART_DM_CR_TX_ENABLE,
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MSM_BOOT_UART_DM_CR(uart_dm_base));
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/* Initialize Receive Path */
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msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
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return 0;
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}
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/**
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* uart_dm_init - initializes UART
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*
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* Initializes clocks, GPIO and UART controller.
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*/
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static int uart_dm_init(void)
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{
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unsigned int dm_base, gsbi_base;
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dm_base = gboard_param->uart_dm_base;
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gsbi_base = gboard_param->uart_gsbi_base;
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ipq_configure_gpio(gboard_param->dbg_uart_gpio, NO_OF_DBG_UART_GPIOS);
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/* Configure the uart clock */
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uart_clock_config(gboard_param->uart_gsbi,
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gboard_param->mnd_value.m_value,
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gboard_param->mnd_value.n_value,
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gboard_param->mnd_value.d_value,
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gboard_param->clk_dummy);
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writel(GSBI_PROTOCOL_CODE_I2C_UART <<
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GSBI_CTRL_REG_PROTOCOL_CODE_S,
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GSBI_CTRL_REG(gsbi_base));
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writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base));
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/* Intialize UART_DM */
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msm_boot_uart_dm_init(dm_base);
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return 0;
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}
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/**
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* ipq806x_serial_putc - transmits a character
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* @c: character to transmit
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*/
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static void ipq806x_serial_putc(char c)
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{
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msm_boot_uart_dm_write(&c, 1);
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}
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/**
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* ipq806x_serial_puts - transmits a string of data
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* @s: string to transmit
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*/
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static void ipq806x_serial_puts(const char *s)
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{
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while (*s != '\0')
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serial_putc(*s++);
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}
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/**
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* ipq806x_serial_tstc - checks if data available for reading
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*
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* Returns 1 if data available, 0 otherwise
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*/
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static int ipq806x_serial_tstc(void)
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{
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/* Return if data is already read */
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if (valid_data)
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return 1;
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/* Read data from the FIFO */
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if (msm_boot_uart_dm_read(&word, &valid_data, 0) != MSM_BOOT_UART_DM_E_SUCCESS)
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return 0;
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return 1;
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}
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/**
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* ipq806x_serial_getc - reads a character
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*
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* Returns the character read from serial port.
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*/
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static int ipq806x_serial_getc(void)
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{
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int byte;
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while (!serial_tstc()) {
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/* wait for incoming data */
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}
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byte = (int)word & 0xff;
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word = word >> 8;
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valid_data--;
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return byte;
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}
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static struct serial_device ipq_serial_device = {
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.name = "ipq_serial",
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.start = uart_dm_init,
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.getc = ipq806x_serial_getc,
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.tstc = ipq806x_serial_tstc,
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.putc = ipq806x_serial_putc,
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.puts = ipq806x_serial_puts,
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||||
};
|
||||
|
||||
__weak struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &ipq_serial_device;
|
||||
}
|
||||
|
||||
/**
|
||||
* ipq806x_serial_init - initializes serial controller
|
||||
*/
|
||||
void ipq806x_serial_initialize(void)
|
||||
{
|
||||
serial_register(&ipq_serial_device);
|
||||
}
|
Reference in New Issue
Block a user