soc/intel/quark: Add temperature sensor support
Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I6dc68c735375c9d1777693264674521f67397556 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14565 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@@ -17,9 +17,104 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <soc/ramstage.h>
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#include <soc/reg_access.h>
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/* Cat Trip Clear value must be less than Cat Trip Set value */
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#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105
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#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65
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static const struct reg_script thermal_init_script[] = {
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/* Setup RMU Thermal sensor registers for Ratiometric mode. */
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REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG,
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~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK
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| B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK
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| B_TSCGF1_CONFIG_ISNSINTERNALVREFEN
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| B_TSCGF1_CONFIG_IBGEN
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| B_TSCGF1_CONFIG_IBGCHOPEN),
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((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE
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<< B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP)
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| (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE
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<< B_TSCGF1_CONFIG_ISNSCHOPSEL_BP)
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| (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE
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<< B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP)
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| (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE
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<< B_TSCGF1_CONFIG_IBGEN_BP)
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| (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE
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<< B_TSCGF1_CONFIG_IBGCHOPEN_BP))),
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REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2,
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~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK
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| B_TSCGF2_CONFIG2_ISPARECTRL_MASK
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| B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK),
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((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE
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<< B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP)
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| (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE
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<< B_TSCGF2_CONFIG2_ISPARECTRL_BP)
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| (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE
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<< B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))),
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REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG,
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~(B_TSCGF2_CONFIG_IDSCONTROL_MASK
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| B_TSCGF2_CONFIG_IDSTIMING_MASK),
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((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE
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<< B_TSCGF2_CONFIG_IDSCONTROL_BP)
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| (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE
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<< B_TSCGF2_CONFIG_IDSTIMING_BP))),
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REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
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~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK,
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V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE
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<< B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP),
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/* Enable RMU Thermal sensor with a Catastrophic Trip point. */
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/* Set up Catastrophic Trip point.
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*
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* Trip Register fields are 8-bit temperature values of granularity 1
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* degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds
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* to 205 degrees C.
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*
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* Add 50 to Celsius values to get values for register fields.
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*/
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REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP,
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~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK),
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(((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50)
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<< TS_CAT_TRIP_SET_THOLD_BP)
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| ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50)
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<< TS_CAT_TRIP_CLEAR_THOLD_BP))),
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/* To enable the TS do the following:
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* 1) Take the TS out of reset by setting itsrst to 0x0.
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* 2) Enable the TS using RMU Thermal sensor mode register.
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*/
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REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
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~B_TSCGF3_CONFIG_ITSRST),
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REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE),
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/* Lock all RMU Thermal sensor control & trip point registers. */
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REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE
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| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE),
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REG_SCRIPT_END
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};
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static void chip_init(void *chip_info)
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{
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/* Validate the temperature settings */
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ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
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ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
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> PLATFORM_CATASTROPHIC_CLEAR_CELSIUS);
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/* Set the temperature settings */
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reg_script_run(thermal_init_script);
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/* Verify that the thermal configuration is locked */
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ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG)
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& (TS_LOCK_THRM_CTRL_REGS_ENABLE
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| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE))
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== (TS_LOCK_THRM_CTRL_REGS_ENABLE
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| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
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/* Perform silicon specific init. */
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if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
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intel_silicon_init();
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