compiler.h: add __weak macro

Instead of writing out '__attribute__((weak))' use a shorter form.

Change-Id: If418a1d55052780077febd2d8f2089021f414b91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Justin TerAvest <teravest@chromium.org>

src/arch/arm/stages.c

@@ -26,11 +26,12 @@
 
 #include <arch/stages.h>
 #include <arch/cache.h>
+#include <compiler.h>
 
 /**
  * generic stage entry point. override this if board specific code is needed.
  */
-__attribute__((weak)) void stage_entry(void)
+__weak void stage_entry(void)
 {
 	main();
 }

src/arch/arm64/arm_tf.c

@@ -21,6 +21,7 @@
 #include <assert.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <program_loading.h>
 
 /*
@@ -36,7 +37,7 @@ static entry_point_info_t bl32_ep_info;
 static entry_point_info_t bl33_ep_info;
 static bl31_params_t bl31_params;
 
-void __attribute__((weak)) *soc_get_bl31_plat_params(bl31_params_t *params)
+void __weak *soc_get_bl31_plat_params(bl31_params_t *params)
 {
 	/* Default weak implementation. */
 	return NULL;

src/arch/arm64/boot.c

@@ -19,6 +19,7 @@
 #include <arch/transition.h>
 #include <arm_tf.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <program_loading.h>
 #include <rules.h>
@@ -78,7 +79,7 @@ int arch_supports_bounce_buffer(void)
 }
 
 /* Generic stage entry point. Can be overridden by board/SoC if needed. */
-__attribute__((weak)) void stage_entry(void)
+__weak void stage_entry(void)
 {
 	main();
 }

src/arch/arm64/transition.c

@@ -17,6 +17,7 @@
 #include <arch/lib_helpers.h>
 #include <arch/transition.h>
 #include <assert.h>
+#include <compiler.h>
 #include <console/console.h>
 
 /* Litte-endian, No XN-forced, Instr cache disabled,
@@ -27,7 +28,7 @@
 		     SCTLR_CACHE_DISABLE | SCTLR_SAE_DISABLE | SCTLR_RES1 | \
 		     SCTLR_ICE_DISABLE | SCTLR_WXN_DISABLE | SCTLR_LITTLE_END)
 
-void __attribute__((weak)) exc_dispatch(struct exc_state *exc_state, uint64_t id)
+void __weak exc_dispatch(struct exc_state *exc_state, uint64_t id)
 {
 	/* Default weak implementation does nothing. */
 }

src/arch/x86/acpi.c

@@ -44,6 +44,7 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <cpu/x86/lapic_def.h>
 #include <cpu/cpu.h>
 #include <cbfs.h>
@@ -971,7 +972,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 }
 #endif
 
-unsigned long __attribute__((weak)) fw_cfg_acpi_tables(unsigned long start)
+unsigned long __weak fw_cfg_acpi_tables(unsigned long start)
 {
 	return 0;
 }
@@ -1238,7 +1239,7 @@ void acpi_save_gnvs(u32 gnvs_address)
 		*gnvs = gnvs_address;
 }
 
-__attribute__((weak)) int acpi_get_gpe(int gpe)
+__weak int acpi_get_gpe(int gpe)
 {
 	return -1; /* implemented by SOC */
 }

src/arch/x86/acpi_s3.c

@@ -17,6 +17,7 @@
 #include <string.h>
 #include <arch/acpi.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <cpu/cpu.h>
 #include <fallback.h>
 #include <timestamp.h>
@@ -218,7 +219,7 @@ static void acpi_jump_to_wakeup(void *vector)
 	acpi_do_wakeup((uintptr_t)vector, source, target, size);
 }
 
-void __attribute__((weak)) mainboard_suspend_resume(void)
+void __weak mainboard_suspend_resume(void)
 {
 }
 

src/arch/x86/acpigen.c

@@ -28,6 +28,7 @@
 #include <lib.h>
 #include <string.h>
 #include <arch/acpigen.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <device/device.h>
 
@@ -1504,28 +1505,28 @@ void acpigen_write_rom(void *bios, const size_t length)
 
 
 /* Soc-implemented functions -- weak definitions. */
-int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned int gpio_num)
+int __weak acpigen_soc_read_rx_gpio(unsigned int gpio_num)
 {
 	printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__);
 	acpigen_write_debug_string("read_rx_gpio not available");
 	return -1;
 }
 
-int __attribute__((weak)) acpigen_soc_get_tx_gpio(unsigned int gpio_num)
+int __weak acpigen_soc_get_tx_gpio(unsigned int gpio_num)
 {
 	printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__);
 	acpigen_write_debug_string("get_tx_gpio not available");
 	return -1;
 }
 
-int __attribute__((weak)) acpigen_soc_set_tx_gpio(unsigned int gpio_num)
+int __weak acpigen_soc_set_tx_gpio(unsigned int gpio_num)
 {
 	printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__);
 	acpigen_write_debug_string("set_tx_gpio not available");
 	return -1;
 }
 
-int __attribute__((weak)) acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
+int __weak acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
 {
 	printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__);
 	acpigen_write_debug_string("clear_tx_gpio not available");

src/arch/x86/cbmem.c

@@ -14,17 +14,18 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <arch/acpi.h>
 
 #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
 
-void __attribute__((weak)) backup_top_of_low_cacheable(uintptr_t ramtop)
+void __weak backup_top_of_low_cacheable(uintptr_t ramtop)
 {
 	/* Do nothing. Chipset may have implementation to save ramtop in NVRAM.
 	 */
 }
 
-uintptr_t __attribute__((weak)) restore_top_of_low_cacheable(void)
+uintptr_t __weak restore_top_of_low_cacheable(void)
 {
 	return 0;
 }
@@ -43,7 +44,7 @@ void set_late_cbmem_top(uintptr_t ramtop)
 }
 
 /* Top of CBMEM is at highest usable DRAM address below 4GiB. */
-uintptr_t __attribute__((weak)) restore_cbmem_top(void)
+uintptr_t __weak restore_cbmem_top(void)
 {
 	if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT) && ENV_ROMSTAGE)
 		if (!acpi_is_wakeup_s3())

src/arch/x86/mpspec.c

@@ -17,6 +17,7 @@
 #include <device/path.h>
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
+#include <compiler.h>
 #include <arch/smp/mpspec.h>
 #include <string.h>
 #include <arch/cpu.h>
@@ -523,7 +524,7 @@ void *mptable_finalize(struct mp_config_table *mc)
 	return smp_next_mpe_entry(mc);
 }
 
-unsigned long __attribute__((weak)) write_smp_table(unsigned long addr)
+unsigned long __weak write_smp_table(unsigned long addr)
 {
 	struct drivers_generic_ioapic_config *ioapic_config;
 	struct mp_config_table *mc;

src/arch/x86/pirq_routing.c

@@ -15,12 +15,13 @@
  * GNU General Public License for more details.
  */
 #include <console/console.h>
+#include <compiler.h>
 #include <arch/pirq_routing.h>
 #include <string.h>
 #include <device/pci.h>
 #include <arch/pirq_routing.h>
 
-void __attribute__((weak)) pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS])
+void __weak pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS])
 {
 }
 

src/arch/x86/postcar.c

@@ -15,6 +15,7 @@
 
 #include <arch/cpu.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <main_decl.h>
 #include <program_loading.h>
@@ -24,7 +25,7 @@
  * Systems without a native coreboot cache-as-ram teardown may implement
  * this to use an alternate method.
  */
-__attribute__((weak)) void late_car_teardown(void) { /* do nothing */ }
+__weak void late_car_teardown(void) { /* do nothing */ }
 
 void main(void)
 {

src/arch/x86/smbios.c

@@ -19,6 +19,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <smbios.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <version.h>
 #include <device/device.h>
@@ -330,7 +331,7 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	return t->length + smbios_string_table_len(t->eos);
 }
 
-const char *__attribute__((weak)) smbios_mainboard_bios_version(void)
+const char *__weak smbios_mainboard_bios_version(void)
 {
 	if (strlen(CONFIG_LOCALVERSION))
 		return CONFIG_LOCALVERSION;
@@ -397,53 +398,53 @@ static int smbios_write_type0(unsigned long *current, int handle)
 
 #if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO)
 
-const char *__attribute__((weak)) smbios_mainboard_serial_number(void)
+const char *__weak smbios_mainboard_serial_number(void)
 {
 	return CONFIG_MAINBOARD_SERIAL_NUMBER;
 }
 
-const char *__attribute__((weak)) smbios_mainboard_version(void)
+const char *__weak smbios_mainboard_version(void)
 {
 	return CONFIG_MAINBOARD_VERSION;
 }
 
-const char *__attribute__((weak)) smbios_mainboard_manufacturer(void)
+const char *__weak smbios_mainboard_manufacturer(void)
 {
 	return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
 }
 
-const char *__attribute__((weak)) smbios_mainboard_product_name(void)
+const char *__weak smbios_mainboard_product_name(void)
 {
 	return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME;
 }
 
-void __attribute__((weak)) smbios_mainboard_set_uuid(u8 *uuid)
+void __weak smbios_mainboard_set_uuid(u8 *uuid)
 {
 	/* leave all zero */
 }
 #endif
 
-const char *__attribute__((weak)) smbios_mainboard_asset_tag(void)
+const char *__weak smbios_mainboard_asset_tag(void)
 {
 	return "";
 }
 
-u8 __attribute__((weak)) smbios_mainboard_feature_flags(void)
+u8 __weak smbios_mainboard_feature_flags(void)
 {
 	return 0;
 }
 
-const char *__attribute__((weak)) smbios_mainboard_location_in_chassis(void)
+const char *__weak smbios_mainboard_location_in_chassis(void)
 {
 	return "";
 }
 
-smbios_board_type __attribute__((weak)) smbios_mainboard_board_type(void)
+smbios_board_type __weak smbios_mainboard_board_type(void)
 {
 	return SMBIOS_BOARD_TYPE_UNKNOWN;
 }
 
-const char *__attribute__((weak)) smbios_mainboard_sku(void)
+const char *__weak smbios_mainboard_sku(void)
 {
 	return "";
 }

src/arch/x86/timestamp.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <cpu/x86/tsc.h>
 #include <timestamp.h>
 
@@ -21,7 +22,7 @@ uint64_t timestamp_get(void)
 	return rdtscll();
 }
 
-unsigned long __attribute__((weak)) tsc_freq_mhz(void)
+unsigned long __weak tsc_freq_mhz(void)
 {
 	/* Default to not knowing TSC frequency. cbmem will have to fallback
 	 * on trying to determine it in userspace. */

src/commonlib/storage/sdhci.c

@@ -23,6 +23,7 @@
 #include <commonlib/sd_mmc_ctrlr.h>
 #include <commonlib/sdhci.h>
 #include <commonlib/storage.h>
+#include <compiler.h>
 #include <delay.h>
 #include <endian.h>
 #include <halt.h>
@@ -38,7 +39,7 @@
 			|| (CONFIG_SDHCI_ADMA_IN_ROMSTAGE && ENV_ROMSTAGE) \
 			|| ENV_POSTCAR || ENV_RAMSTAGE)
 
-__attribute__((weak)) void *dma_malloc(size_t length_in_bytes)
+__weak void *dma_malloc(size_t length_in_bytes)
 {
 	return malloc(length_in_bytes);
 }
@@ -278,20 +279,20 @@ static int sdhci_send_command_bounced(struct sd_mmc_ctrlr *ctrlr,
 	return CARD_COMM_ERR;
 }
 
-__attribute__((weak)) void sdhc_log_command(struct mmc_command *cmd)
+__weak void sdhc_log_command(struct mmc_command *cmd)
 {
 }
 
-__attribute__((weak)) void sdhc_log_command_issued(void)
+__weak void sdhc_log_command_issued(void)
 {
 }
 
-__attribute__((weak)) void sdhc_log_response(uint32_t entries,
+__weak void sdhc_log_response(uint32_t entries,
 	uint32_t *response)
 {
 }
 
-__attribute__((weak)) void sdhc_log_ret(int ret)
+__weak void sdhc_log_ret(int ret)
 {
 }
 
@@ -715,7 +716,7 @@ static int sdhci_pre_init(struct sdhci_ctrlr *sdhci_ctrlr)
 	return 0;
 }
 
-__attribute__((weak)) void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr
+__weak void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr
 	*ctrlr)
 {
 }

src/console/die.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <halt.h>
 
@@ -27,7 +28,7 @@
  * EC is capable of controlling LEDs or a buzzer the method can be overwritten
  * in EC directory instead.
  */
-__attribute__ ((weak)) void die_notify(void)
+__weak void die_notify(void)
 {
 }
 

src/console/post.c

@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <elog.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>
@@ -29,7 +30,7 @@
 /* Some mainboards have very nice features beyond just a simple display.
  * They can override this function.
  */
-void __attribute__((weak)) mainboard_post(uint8_t value)
+void __weak mainboard_post(uint8_t value)
 {
 }
 

src/cpu/intel/microcode/microcode.c

@@ -24,6 +24,7 @@
 #else
 #include <arch/cbfs.h>
 #endif
+#include <compiler.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
@@ -209,7 +210,7 @@ void intel_update_microcode_from_cbfs(void)
 }
 
 #if ENV_RAMSTAGE
-__attribute__((weak)) int soc_skip_ucode_update(u32 currrent_patch_id,
+__weak int soc_skip_ucode_update(u32 currrent_patch_id,
 	u32 new_patch_id)
 {
 	return 0;

src/cpu/x86/smm/smihandler.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
@@ -208,13 +209,13 @@ void smi_handler(u32 smm_revision)
  * entries in the modules make sense. Without default implementations the
  * weak relocations w/o a symbol have a 0 address which is where the modules
  * are linked at. */
-int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; }
-void __attribute__((weak)) cpu_smi_handler(unsigned int node,
+int __weak mainboard_io_trap_handler(int smif) { return 0; }
+void __weak cpu_smi_handler(unsigned int node,
 	smm_state_save_area_t *state_save) {}
-void __attribute__((weak)) northbridge_smi_handler(unsigned int node,
+void __weak northbridge_smi_handler(unsigned int node,
 	smm_state_save_area_t *state_save) {}
-void __attribute__((weak)) southbridge_smi_handler(unsigned int node,
+void __weak southbridge_smi_handler(unsigned int node,
 	smm_state_save_area_t *state_save) {}
-void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {}
-int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; }
-void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {}
+void __weak mainboard_smi_gpi(u32 gpi_sts) {}
+int __weak mainboard_smi_apmc(u8 data) { return 0; }
+void __weak mainboard_smi_sleep(u8 slp_typ) {}

src/cpu/x86/smm/smm_module_handler.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <rmodule.h>
@@ -182,10 +183,10 @@ RMODULE_ENTRY(smm_handler_start);
  * entries in the modules make sense. Without default implementations the
  * weak relocations w/o a symbol have a 0 address which is where the modules
  * are linked at. */
-int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; }
-void __attribute__((weak)) cpu_smi_handler(void) {}
-void __attribute__((weak)) northbridge_smi_handler() {}
-void __attribute__((weak)) southbridge_smi_handler() {}
-void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {}
-int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; }
-void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {}
+int __weak mainboard_io_trap_handler(int smif) { return 0; }
+void __weak cpu_smi_handler(void) {}
+void __weak northbridge_smi_handler() {}
+void __weak southbridge_smi_handler() {}
+void __weak mainboard_smi_gpi(u32 gpi_sts) {}
+int __weak mainboard_smi_apmc(u8 data) { return 0; }
+void __weak mainboard_smi_sleep(u8 slp_typ) {}

src/device/pci_rom.c

@@ -19,6 +19,7 @@
 
 #include <console/console.h>
 #include <commonlib/endian.h>
+#include <compiler.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -29,7 +30,7 @@
 #include <arch/acpigen.h>
 
 /* Rmodules don't like weak symbols. */
-u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; }
+u32 __weak map_oprom_vendev(u32 vendev) { return vendev; }
 
 struct rom_header *pci_rom_probe(struct device *dev)
 {

src/drivers/amd/agesa/romstage.c

@@ -18,6 +18,7 @@
 #include <cbmem.h>
 #include <cpu/amd/car.h>
 #include <cpu/x86/bist.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <halt.h>
 #include <program_loading.h>
@@ -43,7 +44,7 @@ void asmlinkage early_all_cores(void)
 	amd_initmmio();
 }
 
-void __attribute__((weak)) platform_once(struct sysinfo *cb)
+void __weak platform_once(struct sysinfo *cb)
 {
 	board_BeforeAgesa(cb);
 }

src/drivers/amd/agesa/state_machine.c

@@ -21,6 +21,7 @@
 #include <bootstate.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <compiler.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -374,24 +375,24 @@ BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, amd_bs_post_device,
 #endif /* ENV_RAMSTAGE */
 
 /* Empty stubs for cases board does not need to override anything. */
-void __attribute__((weak))
+void __weak
 board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { }
-void __attribute__((weak))
+void __weak
 board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) { }
-void __attribute__((weak))
+void __weak
 board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { }
-void __attribute__((weak))
+void __weak
 board_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) { }
-void __attribute__((weak))
+void __weak
 board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) { }
 
-AGESA_STATUS __attribute__((weak))
+AGESA_STATUS __weak
 fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader)
 {
 	return AGESA_SUCCESS;
 }
 
-AGESA_STATUS __attribute__((weak))
+AGESA_STATUS __weak
 fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader)
 {
 	return AGESA_SUCCESS;

src/drivers/elog/gsmi.c

@@ -15,6 +15,7 @@
 
 #include <compiler.h>
 #include <arch/io.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <elog.h>
@@ -48,12 +49,12 @@ struct gsmi_clear_eventlog_param {
 	u32 data_type;
 } __packed;
 
-void __attribute__((weak)) elog_gsmi_cb_platform_log_wake_source(void)
+void __weak elog_gsmi_cb_platform_log_wake_source(void)
 {
 	/* Default weak implementation, does nothing. */
 }
 
-void __attribute__((weak)) elog_gsmi_cb_mainboard_log_wake_source(void)
+void __weak elog_gsmi_cb_mainboard_log_wake_source(void)
 {
 	/* Default weak implementation, does nothing. */
 }

src/drivers/i2c/tpm/cr50.c

@@ -31,6 +31,7 @@
 
 #include <arch/early_variables.h>
 #include <commonlib/endian.h>
+#include <compiler.h>
 #include <stdint.h>
 #include <string.h>
 #include <types.h>
@@ -58,7 +59,7 @@ struct tpm_inf_dev {
 
 static struct tpm_inf_dev g_tpm_dev CAR_GLOBAL;
 
-__attribute__((weak)) int tis_plat_irq_status(void)
+__weak int tis_plat_irq_status(void)
 {
 	static int warning_displayed CAR_GLOBAL;
 

src/drivers/intel/fsp1_1/car.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/early_variables.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <fsp/car.h>
 #include <fsp/util.h>
@@ -100,18 +101,18 @@ asmlinkage void after_cache_as_ram(void *chipset_context)
 	after_cache_as_ram_stage();
 }
 
-void __attribute__((weak)) car_mainboard_pre_console_init(void)
+void __weak car_mainboard_pre_console_init(void)
 {
 }
 
-void __attribute__((weak)) car_soc_pre_console_init(void)
+void __weak car_soc_pre_console_init(void)
 {
 }
 
-void __attribute__((weak)) car_mainboard_post_console_init(void)
+void __weak car_mainboard_post_console_init(void)
 {
 }
 
-void __attribute__((weak)) car_soc_post_console_init(void)
+void __weak car_soc_post_console_init(void)
 {
 }

src/drivers/intel/fsp1_1/raminit.c

@@ -15,6 +15,7 @@
 
 #include <arch/acpi.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <fsp/memmap.h>
 #include <fsp/romstage.h>
@@ -296,7 +297,7 @@ void raminit(struct romstage_params *params)
 }
 
 /* Initialize the UPD parameters for MemoryInit */
-__attribute__((weak)) void mainboard_memory_init_params(
+__weak void mainboard_memory_init_params(
 	struct romstage_params *params,
 	MEMORY_INIT_UPD *upd_ptr)
 {
@@ -304,7 +305,7 @@ __attribute__((weak)) void mainboard_memory_init_params(
 }
 
 /* Display the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_display_memory_init_params(
+__weak void soc_display_memory_init_params(
 	const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
 {
 	printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
@@ -312,7 +313,7 @@ __attribute__((weak)) void soc_display_memory_init_params(
 }
 
 /* Initialize the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_memory_init_params(
+__weak void soc_memory_init_params(
 	struct romstage_params *params,
 	MEMORY_INIT_UPD *upd)
 {

src/drivers/intel/fsp1_1/ramstage.c

@@ -18,6 +18,7 @@
 #include <arch/acpi.h>
 #include <cbmem.h>
 #include <cbfs.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <fsp/memmap.h>
 #include <fsp/ramstage.h>
@@ -28,7 +29,7 @@
 #include <timestamp.h>
 
 /* SOC initialization after FSP silicon init */
-__attribute__((weak)) void soc_after_silicon_init(void)
+__weak void soc_after_silicon_init(void)
 {
 }
 
@@ -215,13 +216,13 @@ void intel_silicon_init(void)
 }
 
 /* Initialize the UPD parameters for SiliconInit */
-__attribute__((weak)) void mainboard_silicon_init_params(
+__weak void mainboard_silicon_init_params(
 	SILICON_INIT_UPD *params)
 {
 };
 
 /* Display the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_display_silicon_init_params(
+__weak void soc_display_silicon_init_params(
 	const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
 {
 	printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
@@ -229,6 +230,6 @@ __attribute__((weak)) void soc_display_silicon_init_params(
 }
 
 /* Initialize the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params)
+__weak void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
 }

src/drivers/intel/fsp1_1/romstage.c

@@ -20,6 +20,7 @@
 #include <arch/cbfs.h>
 #include <arch/early_variables.h>
 #include <assert.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/intel/microcode.h>
@@ -185,13 +186,13 @@ void after_cache_as_ram_stage(void)
 }
 
 /* Initialize the power state */
-__attribute__((weak)) struct chipset_power_state *fill_power_state(void)
+__weak struct chipset_power_state *fill_power_state(void)
 {
 	return NULL;
 }
 
 /* Board initialization before and after RAM is enabled */
-__attribute__((weak)) void mainboard_romstage_entry(
+__weak void mainboard_romstage_entry(
 	struct romstage_params *params)
 {
 	post_code(0x31);
@@ -201,7 +202,7 @@ __attribute__((weak)) void mainboard_romstage_entry(
 }
 
 /* Save the DIMM information for SMBIOS table 17 */
-__attribute__((weak)) void mainboard_save_dimm_info(
+__weak void mainboard_save_dimm_info(
 	struct romstage_params *params)
 {
 	int channel;
@@ -330,7 +331,7 @@ __attribute__((weak)) void mainboard_save_dimm_info(
 }
 
 /* Add any mainboard specific information */
-__attribute__((weak)) void mainboard_add_dimm_info(
+__weak void mainboard_add_dimm_info(
 	struct romstage_params *params,
 	struct memory_info *mem_info,
 	int channel, int dimm, int index)
@@ -338,44 +339,44 @@ __attribute__((weak)) void mainboard_add_dimm_info(
 }
 
 /* Get the memory configuration data */
-__attribute__((weak)) int mrc_cache_get_current(int type, uint32_t version,
+__weak int mrc_cache_get_current(int type, uint32_t version,
 				struct region_device *rdev)
 {
 	return -1;
 }
 
 /* Save the memory configuration data */
-__attribute__((weak)) int mrc_cache_stash_data(int type, uint32_t version,
+__weak int mrc_cache_stash_data(int type, uint32_t version,
 					const void *data, size_t size)
 {
 	return -1;
 }
 
 /* Transition RAM from off or self-refresh to active */
-__attribute__((weak)) void raminit(struct romstage_params *params)
+__weak void raminit(struct romstage_params *params)
 {
 	post_code(0x34);
 	die("ERROR - No RAM initialization specified!\n");
 }
 
 /* Display the memory configuration */
-__attribute__((weak)) void report_memory_config(void)
+__weak void report_memory_config(void)
 {
 }
 
 /* Choose top of stack and setup MTRRs */
-__attribute__((weak)) void *setup_stack_and_mtrrs(void)
+__weak void *setup_stack_and_mtrrs(void)
 {
 	die("ERROR - Must specify top of stack!\n");
 	return NULL;
 }
 
 /* SOC initialization after RAM is enabled */
-__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
+__weak void soc_after_ram_init(struct romstage_params *params)
 {
 }
 
 /* SOC initialization before RAM is enabled */
-__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
+__weak void soc_pre_ram_init(struct romstage_params *params)
 {
 }

src/drivers/intel/fsp2_0/graphics.c

@@ -124,7 +124,7 @@ int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
 	return 0;
 }
 
-__attribute__((weak)) uintptr_t fsp_soc_get_igd_bar(void)
+__weak uintptr_t fsp_soc_get_igd_bar(void)
 {
 	return 0;
 }

src/drivers/intel/fsp2_0/hob_display.c

@@ -157,7 +157,7 @@ const char *fsp_get_guid_name(const uint8_t *guid)
 	return "Unknown GUID";
 }
 
-__attribute__((weak)) const char *soc_get_hob_type_name(
+__weak const char *soc_get_hob_type_name(
 	const struct hob_header *hob)
 {
 	return NULL;
@@ -173,7 +173,7 @@ void fsp_print_guid_extension_hob(const struct hob_header *hob)
 	printk(BIOS_SPEW, ": %s\n", fsp_get_guid_name(res->owner_guid));
 }
 
-__attribute__((weak)) const char *soc_get_guid_name(const uint8_t *guid)
+__weak const char *soc_get_guid_name(const uint8_t *guid)
 {
 	return NULL;
 }
@@ -212,6 +212,6 @@ void fsp_display_hobs(void)
 	}
 }
 
-__attribute__((weak)) void soc_display_hob(const struct hob_header *hob)
+__weak void soc_display_hob(const struct hob_header *hob)
 {
 }

src/drivers/intel/fsp2_0/memory_init.c

@@ -307,13 +307,13 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
 	return CB_SUCCESS;
 }
 
-__attribute__((weak))
+__weak
 uint8_t fsp_memory_mainboard_version(void)
 {
 	return 0;
 }
 
-__attribute__((weak))
+__weak
 uint8_t fsp_memory_soc_version(void)
 {
 	return 0;

src/drivers/intel/fsp2_0/notify.c

@@ -12,6 +12,7 @@
 
 #include <arch/cpu.h>
 #include <bootstate.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <soc/intel/common/util.h>
@@ -87,7 +88,7 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
 						(void *) READY_TO_BOOT);
 
-__attribute__((weak)) void platform_fsp_notify_status(
+__weak void platform_fsp_notify_status(
 	enum fsp_notify_phase phase)
 {
 }

src/drivers/intel/fsp2_0/upd_display.c

@@ -10,6 +10,7 @@
  */
 
 #include <arch/cpu.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <lib.h>
@@ -50,7 +51,7 @@ static void fspm_display_arch_params(const FSPM_ARCH_UPD *old,
 }
 
 /* Display the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_display_fspm_upd_params(
+__weak void soc_display_fspm_upd_params(
 	const FSPM_UPD *fspm_old_upd,
 	const FSPM_UPD *fspm_new_upd)
 {
@@ -67,7 +68,7 @@ void fspm_display_upd_values(const FSPM_UPD *old,
 }
 
 /* Display the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_display_fsps_upd_params(
+__weak void soc_display_fsps_upd_params(
 	const FSPS_UPD *fsps_old_upd,
 	const FSPS_UPD *fsps_new_upd)
 {

src/drivers/intel/wifi/wifi.c

@@ -64,7 +64,7 @@ static int smbios_write_wifi(struct device *dev, int *handle,
 }
 #endif
 
-__attribute__((weak))
+__weak
 int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits)
 {
 	return -1;

src/drivers/spi/spi-generic.c

@@ -15,6 +15,7 @@
  */
 
 #include <assert.h>
+#include <compiler.h>
 #include <spi-generic.h>
 #include <string.h>
 
@@ -116,7 +117,7 @@ unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len,
 	return min(ctrlr_max, buf_len);
 }
 
-void __attribute__((weak)) spi_init(void)
+void __weak spi_init(void)
 {
 	/* Default weak implementation - do nothing. */
 }

src/drivers/spi/tpm/tpm.c

@@ -17,6 +17,7 @@
 
 #include <arch/early_variables.h>
 #include <assert.h>
+#include <compiler.h>
 #include <commonlib/endian.h>
 #include <console/console.h>
 #include <delay.h>
@@ -64,7 +65,7 @@ void tpm2_get_info(struct tpm2_info *info)
 	*info = car_get_var(g_tpm_info);
 }
 
-__attribute__((weak)) int tis_plat_irq_status(void)
+__weak int tis_plat_irq_status(void)
 {
 	static int warning_displayed CAR_GLOBAL;
 

src/ec/google/chromeec/crosec_proto.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <delay.h>
 #include <stdint.h>
@@ -23,7 +24,7 @@
 #include "ec_message.h"
 
 /* Common utilities */
-void * __attribute__((weak)) crosec_get_buffer(size_t size, int req)
+void * __weak crosec_get_buffer(size_t size, int req)
 {
 	printk(BIOS_DEBUG, "crosec_get_buffer() implementation required.\n");
 	return NULL;

src/include/compiler.h

@@ -25,5 +25,6 @@
 #define __aligned(x) __attribute__((aligned(x)))
 #define __always_unused __attribute__((unused))
 #define __must_check __attribute__((warn_unused_result))
+#define __weak __attribute__((weak))
 
 #endif

src/lib/boot_device.c

@@ -14,8 +14,9 @@
  */
 
 #include <boot_device.h>
+#include <compiler.h>
 
-void __attribute__((weak)) boot_device_init(void)
+void __weak boot_device_init(void)
 {
 	/* Provide weak do-nothing init. */
 }

src/lib/bootblock.c

@@ -16,6 +16,7 @@
 
 #include <arch/exception.h>
 #include <bootblock_common.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <delay.h>
 #include <pc80/mc146818rtc.h>
@@ -25,10 +26,10 @@
 
 DECLARE_OPTIONAL_REGION(timestamp);
 
-__attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ }
-__attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ }
-__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ }
-__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ }
+__weak void bootblock_mainboard_early_init(void) { /* no-op */ }
+__weak void bootblock_soc_early_init(void) { /* do nothing */ }
+__weak void bootblock_soc_init(void) { /* do nothing */ }
+__weak void bootblock_mainboard_init(void) { /* do nothing */ }
 
 asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp)
 {

src/lib/cbfs.c

@@ -20,6 +20,7 @@
 #include <boot_device.h>
 #include <cbfs.h>
 #include <commonlib/compression.h>
+#include <compiler.h>
 #include <endian.h>
 #include <lib.h>
 #include <symbols.h>
@@ -308,7 +309,7 @@ static int cbfs_master_header_props(struct cbfs_props *props)
 /* This struct is marked as weak to allow a particular platform to
  * override the master header logic. This implementation should work for most
  * devices. */
-const struct cbfs_locator __attribute__((weak)) cbfs_master_header_locator = {
+const struct cbfs_locator __weak cbfs_master_header_locator = {
 	.name = "Master Header Locator",
 	.locate = cbfs_master_header_props,
 };

src/lib/cbmem_common.c

@@ -14,6 +14,7 @@
  */
 #include <console/console.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <bootstate.h>
 #include <rules.h>
 #include <symbols.h>
@@ -37,7 +38,7 @@ void cbmem_run_init_hooks(int is_recovery)
 	}
 }
 
-void __attribute__((weak)) cbmem_fail_resume(void)
+void __weak cbmem_fail_resume(void)
 {
 }
 

src/lib/coreboot_table.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/cbconfig.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <console/uart.h>
 #include <ip_checksum.h>
@@ -244,9 +245,9 @@ static inline void lb_vboot_handoff(struct lb_header *header) {}
 #endif /* CONFIG_VBOOT */
 #endif /* CONFIG_CHROMEOS */
 
-__attribute__((weak)) uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; }
-__attribute__((weak)) uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; }
-__attribute__((weak)) uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; }
+__weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; }
+__weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; }
+__weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; }
 
 static void lb_board_id(struct lb_header *header)
 {
@@ -441,7 +442,7 @@ static void lb_record_version_timestamp(struct lb_header *header)
 	rec->timestamp = coreboot_version_timestamp;
 }
 
-void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ }
+void __weak lb_board(struct lb_header *header) { /* NOOP */ }
 
 /*
  * It's possible that the system is using a SPI flash as the boot device,
@@ -449,7 +450,7 @@ void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ }
  * case don't provide any information as the correct information is
  * not known.
  */
-void __attribute__((weak)) lb_spi_flash(struct lb_header *header) { /* NOOP */ }
+void __weak lb_spi_flash(struct lb_header *header) { /* NOOP */ }
 
 static struct lb_forward *lb_forward(struct lb_header *header,
 	struct lb_header *next_header)

src/lib/fallback_boot.c

@@ -1,8 +1,9 @@
 #include <fallback.h>
+#include <compiler.h>
 #include <watchdog.h>
 
 /* Implement platform specific override. */
-void __attribute__((weak)) set_boot_successful(void) { }
+void __weak set_boot_successful(void) { }
 
 void boot_successful(void)
 {

src/lib/gpio.c

@@ -15,6 +15,7 @@
 
 #include <assert.h>
 #include <base3.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <delay.h>
 #include <gpio.h>
@@ -168,13 +169,13 @@ int _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first)
 }
 
 /* Default handler for ACPI path is to return NULL */
-__attribute__((weak)) const char *gpio_acpi_path(gpio_t gpio)
+__weak const char *gpio_acpi_path(gpio_t gpio)
 {
 	return NULL;
 }
 
 /* Default handler returns 0 because type of gpio_t is unknown */
-__attribute__((weak)) uint16_t gpio_acpi_pin(gpio_t gpio)
+__weak uint16_t gpio_acpi_pin(gpio_t gpio)
 {
 	return 0;
 }

src/lib/hardwaremain.c

@@ -21,6 +21,7 @@
 #include <adainit.h>
 #include <arch/exception.h>
 #include <bootstate.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <console/post_codes.h>
 #include <cbmem.h>
@@ -115,7 +116,7 @@ static struct boot_state boot_states[] = {
 	BS_INIT_ENTRY(BS_PAYLOAD_BOOT, bs_payload_boot),
 };
 
-void __attribute__((weak)) arch_bootstate_coreboot_exit(void) { }
+void __weak arch_bootstate_coreboot_exit(void) { }
 
 static boot_state_t bs_pre_device(void *arg)
 {

src/lib/imd_cbmem.c

@@ -15,6 +15,7 @@
 
 #include <bootstate.h>
 #include <bootmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <imd.h>
@@ -109,7 +110,7 @@ void cbmem_initialize_empty(void)
 	cbmem_initialize_empty_id_size(0, 0);
 }
 
-void __attribute__((weak)) cbmem_top_init(void)
+void __weak cbmem_top_init(void)
 {
 }
 

src/lib/prog_loaders.c

@@ -17,6 +17,7 @@
 #include <stdlib.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <fallback.h>
 #include <halt.h>
@@ -71,9 +72,9 @@ fail:
 	halt();
 }
 
-void __attribute__((weak)) stage_cache_add(int stage_id,
+void __weak stage_cache_add(int stage_id,
 						const struct prog *stage) {}
-void __attribute__((weak)) stage_cache_load_stage(int stage_id,
+void __weak stage_cache_load_stage(int stage_id,
 							struct prog *stage) {}
 
 static void ramstage_cache_invalid(void)
@@ -164,7 +165,7 @@ fail:
 static struct prog global_payload =
 	PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload");
 
-void __attribute__((weak)) mirror_payload(struct prog *payload)
+void __weak mirror_payload(struct prog *payload)
 {
 }
 

src/lib/prog_ops.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <program_loading.h>
 
 /* For each segment of a program loaded this function is called*/
@@ -23,13 +24,13 @@ void prog_segment_loaded(uintptr_t start, size_t size, int flags)
 	arch_segment_loaded(start, size, flags);
 }
 
-void __attribute__((weak)) platform_segment_loaded(uintptr_t start,
+void __weak platform_segment_loaded(uintptr_t start,
 							size_t size, int flags)
 {
 	/* do nothing */
 }
 
-void __attribute__((weak)) arch_segment_loaded(uintptr_t start, size_t size,
+void __weak arch_segment_loaded(uintptr_t start, size_t size,
 						int flags)
 {
 	/* do nothing */
@@ -41,7 +42,7 @@ void prog_run(struct prog *prog)
 	arch_prog_run(prog);
 }
 
-void __attribute__((weak)) platform_prog_run(struct prog *prog)
+void __weak platform_prog_run(struct prog *prog)
 {
 	/* do nothing */
 }

src/lib/reset.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/cache.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <halt.h>
 #include <reset.h>
@@ -27,10 +28,10 @@ __attribute__((noreturn)) static void __hard_reset(void) {
 }
 
 /* Not all platforms implement all reset types. Fall back to hard_reset. */
-__attribute__((weak)) void do_global_reset(void) { __hard_reset(); }
-__attribute__((weak)) void do_soft_reset(void) { __hard_reset(); }
+__weak void do_global_reset(void) { __hard_reset(); }
+__weak void do_soft_reset(void) { __hard_reset(); }
 
-__attribute__((weak)) void soc_reset_prepare(enum reset_type rt) { /* no-op */ }
+__weak void soc_reset_prepare(enum reset_type rt) { /* no-op */ }
 
 void global_reset(void)
 {

src/lib/timer.c

@@ -13,12 +13,13 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <console/console.h>
 #include <timer.h>
 #include <delay.h>
 #include <thread.h>
 
-__attribute__((weak)) void init_timer(void) { /* do nothing */ }
+__weak void init_timer(void) { /* do nothing */ }
 
 void udelay(unsigned int usec)
 {

src/lib/timestamp.c

@@ -361,7 +361,7 @@ ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem)
 RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem)
 
 /* Provide default timestamp implementation using monotonic timer. */
-uint64_t  __attribute__((weak)) timestamp_get(void)
+uint64_t  __weak timestamp_get(void)
 {
 	struct mono_time t1, t2;
 
@@ -375,7 +375,7 @@ uint64_t  __attribute__((weak)) timestamp_get(void)
 }
 
 /* Like timestamp_get() above this matches up with microsecond granularity. */
-int __attribute__((weak)) timestamp_tick_freq_mhz(void)
+int __weak timestamp_tick_freq_mhz(void)
 {
 	return 1;
 }

src/lib/wrdd.c

@@ -14,9 +14,10 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <wrdd.h>
 
-uint16_t __attribute__((weak)) wifi_regulatory_domain(void)
+uint16_t __weak wifi_regulatory_domain(void)
 {
 	return WRDD_DEFAULT_REGULATORY_DOMAIN;
 }

src/mainboard/google/cyan/romstage.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <soc/romstage.h>
 #include <baseboard/variants.h>
 #include <chip.h>
@@ -47,7 +48,7 @@ void mainboard_memory_init_params(struct romstage_params *params,
 	variant_memory_init_params(memory_params);
 }
 
-__attribute__ ((weak))
+__weak
 void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
 {
 }

src/mainboard/google/cyan/spd/spd.c

@@ -16,6 +16,7 @@
 
 #include <cbfs.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <gpio.h>
 #include <lib.h>
@@ -28,7 +29,7 @@
 #include <spd_bin.h>
 #include "spd_util.h"
 
-__attribute__ ((weak)) uint8_t get_ramid(void)
+__weak uint8_t get_ramid(void)
 {
 	gpio_t spd_gpios[] = {
 		GP_SW_80,	/* SATA_GP3, RAMID0 */

src/mainboard/google/kahlee/mainboard.c

@@ -14,6 +14,7 @@
  */
 
 #include <string.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <arch/acpi.h>
@@ -225,7 +226,7 @@ struct chip_operations mainboard_ops = {
 };
 
 /* Variants may override this function so see definitions in variants/ */
-uint8_t __attribute__((weak)) variant_board_sku(void)
+uint8_t __weak variant_board_sku(void)
 {
 	return 0;
 }

src/mainboard/google/kahlee/romstage.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <amdblocks/dimm_spd.h>
 #include <baseboard/variants.h>
 #include <soc/romstage.h>
@@ -22,7 +23,7 @@ int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len)
 	return variant_mainboard_read_spd(spdAddress, buf, len);
 }
 
-void __attribute__((weak)) variant_romstage_entry(int s3_resume)
+void __weak variant_romstage_entry(int s3_resume)
 {
 	/* By default, don't do anything */
 }

src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <amdblocks/agesawrapper.h>
 #include <variant/gpio.h>
 #include <boardid.h>
@@ -236,7 +237,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieNoBayhub = {
  *
  **/
 /*---------------------------------------------------------------------------*/
-VOID __attribute__((weak)) OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
+VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 {
 	InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
 	InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;

src/mainboard/google/kahlee/variants/baseboard/gpio.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <baseboard/variants.h>
 #include <soc/gpio.h>
 #include <soc/smi.h>
@@ -485,7 +486,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_135, PULL_UP),
 };
 
-const __attribute__((weak))
+const __weak
 struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
 {
 	if (board_id() < 2) {
@@ -497,7 +498,7 @@ struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
 	}
 }
 
-const __attribute__((weak))
+const __weak
 struct soc_amd_gpio *variant_gpio_table(size_t *size)
 {
 	if (board_id() < 2) {
@@ -565,13 +566,13 @@ static const struct sci_source gpe_table[] = {
 	},
 };
 
-const __attribute__((weak)) struct sci_source *get_gpe_table(size_t *num)
+const __weak struct sci_source *get_gpe_table(size_t *num)
 {
 	*num = ARRAY_SIZE(gpe_table);
 	return gpe_table;
 }
 
-int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map)
+int __weak variant_get_xhci_oc_map(uint16_t *map)
 {
 	*map =  USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0/4 = OC0 */
 	*map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1/5 = OC1 */
@@ -580,7 +581,7 @@ int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map)
 	return 0;
 }
 
-int __attribute__((weak)) variant_get_ehci_oc_map(uint16_t *map)
+int __weak variant_get_ehci_oc_map(uint16_t *map)
 {
 	*map = USB_OC_DISABLE_ALL;
 	return 0;

src/mainboard/google/kahlee/variants/baseboard/memory.c

@@ -14,13 +14,14 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <gpio.h> /* src/include/gpio.h */
 #include <spd_bin.h>
 #include <variant/gpio.h>
 #include <amdblocks/dimm_spd.h>
 
-uint8_t __attribute__((weak)) variant_memory_sku(void)
+uint8_t __weak variant_memory_sku(void)
 {
 	gpio_t pads[] = {
 		[3] = MEM_CONFIG3,
@@ -32,7 +33,7 @@ uint8_t __attribute__((weak)) variant_memory_sku(void)
 	return gpio_base2_value(pads, ARRAY_SIZE(pads));
 }
 
-int __attribute__((weak)) variant_mainboard_read_spd(uint8_t spdAddress,
+int __weak variant_mainboard_read_spd(uint8_t spdAddress,
 							char *buf, size_t len)
 {
 	struct region_device spd_rdev;

src/mainboard/google/octopus/variants/baseboard/boardid.c

@@ -13,10 +13,11 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <baseboard/variants.h>
 #include <ec/google/chromeec/ec.h>
 
-uint8_t __attribute__((weak)) variant_board_id(void)
+uint8_t __weak variant_board_id(void)
 {
 	return google_chromeec_get_board_version();
 }

src/mainboard/google/octopus/variants/baseboard/gpio.c

@@ -16,6 +16,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <compiler.h>
 
 /*
  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
@@ -254,7 +255,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 0, DEEP, NONE, HIZCRx0, DISPUPD),
 };
 
-const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
+const struct pad_config *__weak variant_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(gpio_table);
 	return gpio_table;
@@ -280,7 +281,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
 };
 
-const struct pad_config *__attribute__((weak))
+const struct pad_config *__weak
 variant_early_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(early_gpio_table);
@@ -291,7 +292,7 @@ variant_early_gpio_table(size_t *num)
 static const struct pad_config sleep_gpio_table[] = {
 };
 
-const struct pad_config *__attribute__((weak))
+const struct pad_config *__weak
 variant_sleep_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(sleep_gpio_table);
@@ -302,7 +303,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_WP_AH(PAD_SCC(GPIO_PCH_WP), GPIO_COMM_SCC_NAME),
 };
 
-const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
 {
 	*num = ARRAY_SIZE(cros_gpios);
 	return cros_gpios;

src/mainboard/google/octopus/variants/baseboard/memory.c

@@ -14,6 +14,7 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <gpio.h>
 #include <soc/meminit.h>
 #include <variant/gpio.h>
@@ -133,12 +134,12 @@ static const struct lpddr4_cfg lp4cfg = {
 	.swizzle_config = &baseboard_lpddr4_swizzle,
 };
 
-const struct lpddr4_cfg *__attribute__((weak)) variant_lpddr4_config(void)
+const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
 {
 	return &lp4cfg;
 }
 
-size_t __attribute__((weak)) variant_memory_sku(void)
+size_t __weak variant_memory_sku(void)
 {
 	gpio_t pads[] = {
 		[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,

src/mainboard/google/octopus/variants/baseboard/nhlt.c

@@ -14,11 +14,12 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <nhlt.h>
 #include <soc/nhlt.h>
 
-void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+void __weak variant_nhlt_init(struct nhlt *nhlt)
 {
 	/* 2 Channel DMIC array. */
 	if (!nhlt_soc_add_dmic_array(nhlt, 2))

src/mainboard/google/poppy/ramstage.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <baseboard/variants.h>
 #include <soc/ramstage.h>
 
@@ -29,7 +30,7 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 	gpio_configure_pads(pads, num);
 }
 
-void __attribute__((weak)) variant_devtree_update(void)
+void __weak variant_devtree_update(void)
 {
 	/* Override dev tree settings per board */
 }

src/mainboard/google/poppy/variants/baseboard/gpio.c

@@ -16,6 +16,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <compiler.h>
 
 /* Pad configuration in ramstage */
 /* Leave eSPI pins untouched from default settings */
@@ -371,13 +372,13 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
 };
 
-const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
+const struct pad_config * __weak variant_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(gpio_table);
 	return gpio_table;
 }
 
-const struct pad_config * __attribute__((weak))
+const struct pad_config * __weak
 	variant_early_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(early_gpio_table);
@@ -385,7 +386,7 @@ const struct pad_config * __attribute__((weak))
 }
 
 /* override specific gpio by sku id */
-const struct pad_config * __attribute__((weak))
+const struct pad_config * __weak
 	variant_sku_gpio_table(size_t *num)
 {
 	*num = 0;
@@ -397,7 +398,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 };
 
-const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
+const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
 {
 	*num = ARRAY_SIZE(cros_gpios);
 	return cros_gpios;

src/mainboard/google/poppy/variants/baseboard/memory.c

@@ -14,6 +14,7 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <gpio.h>
 #include <variant/gpio.h>
 
@@ -37,7 +38,7 @@ static const u16 rcomp_resistor[] = { 200, 81, 162 };
 /* Rcomp target */
 static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
 
-void __attribute__((weak)) variant_memory_params(struct memory_params *p)
+void __weak variant_memory_params(struct memory_params *p)
 {
 	p->type = MEMORY_LPDDR3;
 	p->dq_map = dq_map;
@@ -50,7 +51,7 @@ void __attribute__((weak)) variant_memory_params(struct memory_params *p)
 	p->rcomp_target_size = sizeof(rcomp_target);
 }
 
-int __attribute__((weak)) variant_memory_sku(void)
+int __weak variant_memory_sku(void)
 {
 	gpio_t spd_gpios[] = {
 		GPIO_MEM_CONFIG_0,

src/mainboard/google/poppy/variants/baseboard/nhlt.c

@@ -14,11 +14,12 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <nhlt.h>
 #include <soc/nhlt.h>
 
-void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+void __weak variant_nhlt_init(struct nhlt *nhlt)
 {
 	/* 2 Channel DMIC array. */
 	if (nhlt_soc_add_dmic_array(nhlt, 2))
@@ -37,7 +38,7 @@ void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
 		printk(BIOS_ERR, "Couldn't add Realtek RT5663.\n");
 }
 
-void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id,
+void __weak variant_nhlt_oem_overrides(const char **oem_id,
 						const char **oem_table_id,
 						uint32_t *oem_revision)
 {

src/mainboard/google/reef/mainboard.c

@@ -16,6 +16,7 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <boardid.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <ec/ec.h>
@@ -30,7 +31,7 @@
 #include <variant/gpio.h>
 
 /* override specific gpio by sku id */
-const struct pad_config __attribute__((weak))
+const struct pad_config __weak
 *variant_sku_gpio_table(size_t *num)
 {
 	*num = 0;
@@ -73,7 +74,7 @@ uint8_t sku_strapping_value(void)
 	return gpio_base3_value(board_sku_gpios, num);
 }
 
-uint8_t __attribute__((weak)) variant_board_sku(void)
+uint8_t __weak variant_board_sku(void)
 {
 	static int board_sku_num = -1;
 
@@ -84,7 +85,7 @@ uint8_t __attribute__((weak)) variant_board_sku(void)
 }
 
 /* Set variant board sku to ec by sku id */
-void __attribute__((weak)) variant_board_ec_set_skuid(void)
+void __weak variant_board_ec_set_skuid(void)
 {
 }
 
@@ -97,7 +98,7 @@ const char *smbios_mainboard_sku(void)
 	return sku_str;
 }
 
-void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id,
+void __weak variant_nhlt_oem_overrides(const char **oem_id,
 						const char **oem_table_id,
 						uint32_t *oem_revision)
 {

src/mainboard/google/reef/variants/baseboard/gpio.c

@@ -16,6 +16,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <compiler.h>
 
 /*
  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
@@ -345,7 +346,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_73, UP_20K, DEEP),	 /* GP_CAMERASB11 */
 };
 
-const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
+const struct pad_config * __weak variant_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(gpio_table);
 	return gpio_table;
@@ -362,7 +363,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPIO_122, 0, DEEP),		 /* SIO_SPI_2_RXD */
 };
 
-const struct pad_config * __attribute__((weak))
+const struct pad_config * __weak
 variant_early_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(early_gpio_table);
@@ -375,7 +376,7 @@ static const struct pad_config sleep_gpio_table[] = {
 	PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP),	/* NFC_INT_L */
 };
 
-const struct pad_config * __attribute__((weak))
+const struct pad_config * __weak
 variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 {
 	*num = ARRAY_SIZE(sleep_gpio_table);
@@ -388,7 +389,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME),
 };
 
-const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
+const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
 {
 	*num = ARRAY_SIZE(cros_gpios);
 	return cros_gpios;

src/mainboard/google/reef/variants/baseboard/memory.c

@@ -14,6 +14,7 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <gpio.h>
 #include <soc/meminit.h>
 #include <variant/gpio.h>
@@ -137,12 +138,12 @@ static const struct lpddr4_cfg lp4cfg = {
 	.swizzle_config = &baseboard_lpddr4_swizzle,
 };
 
-const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void)
+const struct lpddr4_cfg * __weak variant_lpddr4_config(void)
 {
 	return &lp4cfg;
 }
 
-size_t __attribute__((weak)) variant_memory_sku(void)
+size_t __weak variant_memory_sku(void)
 {
 	gpio_t pads[] = {
 		[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,

src/mainboard/google/reef/variants/baseboard/nhlt.c

@@ -14,13 +14,14 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <nhlt.h>
 #include <soc/nhlt.h>
 #include <gpio.h>
 #include <baseboard/gpio.h>
 
-void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+void __weak variant_nhlt_init(struct nhlt *nhlt)
 {
 	/* 1-dmic configuration */
 	if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&

src/mainboard/google/zoombini/memory.c

@@ -15,6 +15,7 @@
 
 #include <baseboard/variants.h>
 #include <baseboard/gpio.h>
+#include <compiler.h>
 #include <gpio.h>
 #include <soc/cnl_lpddr4_init.h>
 
@@ -81,12 +82,12 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
 	.ect = 0,
 };
 
-const struct lpddr4_cfg *__attribute__((weak)) variant_lpddr4_config(void)
+const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
 {
 	return &baseboard_lpddr4_cfg;
 }
 
-size_t __attribute__((weak)) variant_memory_sku(void)
+size_t __weak variant_memory_sku(void)
 {
 	const gpio_t pads[] = {
 		[3] = GPIO_MEM_CONFIG_3, [2] = GPIO_MEM_CONFIG_2,

src/mainboard/google/zoombini/variants/baseboard/boardid.c

@@ -14,9 +14,10 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <ec/google/chromeec/ec.h>
 
-uint8_t __attribute__((weak)) variant_board_id(void)
+uint8_t __weak variant_board_id(void)
 {
 	return google_chromeec_get_board_version();
 }

src/mainboard/google/zoombini/variants/baseboard/gpio.c

@@ -15,6 +15,7 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <compiler.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config gpio_table[] = {
@@ -255,13 +256,13 @@ static const struct pad_config early_gpio_table[] = {
 					 INVERT), /* H1_PCH_INT_ODL */
 };
 
-const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
+const struct pad_config *__weak variant_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(gpio_table);
 	return gpio_table;
 }
 
-const struct pad_config *__attribute__((weak))
+const struct pad_config *__weak
 	variant_early_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(early_gpio_table);
@@ -272,7 +273,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 };
 
-const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
 {
 	*num = ARRAY_SIZE(cros_gpios);
 	return cros_gpios;

src/mainboard/google/zoombini/variants/baseboard/nhlt.c

@@ -14,11 +14,12 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <nhlt.h>
 #include <soc/nhlt.h>
 
-void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+void __weak variant_nhlt_init(struct nhlt *nhlt)
 {
 	/* 1-dmic configuration */
 	if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&

src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c

@@ -16,6 +16,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <compiler.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {
@@ -297,13 +298,13 @@ static const struct pad_config early_gpio_table[] = {
 
 };
 
-const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
+const struct pad_config *__weak variant_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(gpio_table);
 	return gpio_table;
 }
 
-const struct pad_config *__attribute__((weak))
+const struct pad_config *__weak
 	variant_early_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(early_gpio_table);
@@ -314,7 +315,7 @@ static const struct cros_gpio cros_gpios[] = {
         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 };
 
-const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
+const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
 {
         *num = ARRAY_SIZE(cros_gpios);
         return cros_gpios;

src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c

@@ -14,11 +14,12 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <nhlt.h>
 #include <soc/nhlt.h>
 
-void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+void __weak variant_nhlt_init(struct nhlt *nhlt)
 {
 	/* 1-dmic configuration */
 	if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&

src/mainboard/intel/galileo/vboot.c

@@ -14,6 +14,7 @@
 
 #include <assert.h>
 #include <bootmode.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/i2c_simple.h>
@@ -74,7 +75,7 @@ void verstage_mainboard_init(void)
 	reg_script_run(script);
 }
 
-void __attribute__((weak)) vboot_platform_prepare_reboot(void)
+void __weak vboot_platform_prepare_reboot(void)
 {
 	const struct reg_script *script;
 

src/mainboard/intel/glkrvp/chromeos.c

@@ -15,6 +15,7 @@
 
 #include <baseboard/variants.h>
 #include <boot/coreboot_tables.h>
+#include <compiler.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -55,7 +56,7 @@ void mainboard_chromeos_acpi_generate(void)
 	chromeos_acpi_gpio_generate(gpios, num);
 }
 
-int __attribute__((weak)) get_lid_switch(void)
+int __weak get_lid_switch(void)
 {
 	return -1;
 }

src/mainboard/intel/glkrvp/variants/baseboard/boardid.c

@@ -14,9 +14,10 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <ec/google/chromeec/ec.h>
 
-uint8_t __attribute__((weak)) variant_board_id(void)
+uint8_t __weak variant_board_id(void)
 {
 	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
 		return google_chromeec_get_board_version();

src/mainboard/intel/glkrvp/variants/baseboard/gpio.c

@@ -16,6 +16,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <compiler.h>
 
 /*
  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
@@ -250,7 +251,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_STROBE*/
 };
 
-const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
+const struct pad_config * __weak variant_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(gpio_table);
 	return gpio_table;
@@ -262,7 +263,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */
 };
 
-const struct pad_config * __attribute__((weak))
+const struct pad_config * __weak
 variant_early_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(early_gpio_table);
@@ -277,7 +278,7 @@ static const struct pad_config sleep_gpio_table[] = {
 #endif
 };
 
-const struct pad_config * __attribute__((weak))
+const struct pad_config * __weak
 variant_sleep_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(sleep_gpio_table);
@@ -291,7 +292,7 @@ static const struct cros_gpio cros_gpios[] = {
 #endif
 };
 
-const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
+const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
 {
 	*num = ARRAY_SIZE(cros_gpios);
 	return cros_gpios;

src/mainboard/intel/glkrvp/variants/baseboard/memory.c

@@ -14,6 +14,7 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <gpio.h>
 #include <soc/meminit.h>
 #include <variant/gpio.h>
@@ -133,12 +134,12 @@ static const struct lpddr4_cfg lp4cfg = {
 	.swizzle_config = &baseboard_lpddr4_swizzle,
 };
 
-const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void)
+const struct lpddr4_cfg * __weak variant_lpddr4_config(void)
 {
 	return &lp4cfg;
 }
 
-size_t __attribute__((weak)) variant_memory_sku(void)
+size_t __weak variant_memory_sku(void)
 {
 	return 0;
 }

src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c

@@ -14,11 +14,12 @@
  */
 
 #include <baseboard/variants.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <nhlt.h>
 #include <soc/nhlt.h>
 
-void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+void __weak variant_nhlt_init(struct nhlt *nhlt)
 {
 	/* 1-dmic configuration */
 	if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&

src/mainboard/siemens/mc_apl1/gpio.c

@@ -16,6 +16,7 @@
 
 #include <soc/gpio.h>
 #include <commonlib/helpers.h>
+#include <compiler.h>
 #include "brd_gpio.h"
 
 /*
@@ -363,7 +364,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1),	/* SVID0_CLK */
 };
 
-const struct pad_config *__attribute__((weak)) brd_gpio_table(size_t *num)
+const struct pad_config *__weak brd_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(gpio_table);
 	return gpio_table;
@@ -406,7 +407,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),	/* LPC_FRAME_N */
 };
 
-const struct pad_config *__attribute__((weak))
+const struct pad_config *__weak
 brd_early_gpio_table(size_t *num)
 {
 	*num = ARRAY_SIZE(early_gpio_table);

src/northbridge/amd/pi/agesawrapper.c

@@ -16,6 +16,7 @@
 #include <AGESA.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <delay.h>
 #include <cpu/x86/mtrr.h>
 #include <FchPlatform.h>
@@ -25,7 +26,7 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 
-void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {}
+void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {}
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 

src/security/vboot/bootmode.c

@@ -17,6 +17,7 @@
 #include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <rules.h>
 #include <string.h>
 #include <vb2_api.h>
@@ -141,18 +142,18 @@ int vboot_recovery_mode_enabled(void)
 	return !!vboot_check_recovery_request();
 }
 
-int __attribute__((weak)) clear_recovery_mode_switch(void)
+int __weak clear_recovery_mode_switch(void)
 {
 	// Weak implementation. Nothing to do.
 	return 0;
 }
 
-void __attribute__((weak)) log_recovery_mode_switch(void)
+void __weak log_recovery_mode_switch(void)
 {
 	// Weak implementation. Nothing to do.
 }
 
-int __attribute__((weak)) get_recovery_mode_retrain_switch(void)
+int __weak get_recovery_mode_retrain_switch(void)
 {
 	return 0;
 }
@@ -175,12 +176,12 @@ int vboot_developer_mode_enabled(void)
  * TODO: Create flash protection interface which implements get_write_protect_state.
  * get_recovery_mode_switch should be implemented as default function.
  */
-int __attribute__((weak)) get_write_protect_state(void)
+int __weak get_write_protect_state(void)
 {
 	return 0;
 }
 
-int __attribute__((weak)) get_recovery_mode_switch(void)
+int __weak get_recovery_mode_switch(void)
 {
 	return 0;
 }

src/security/vboot/vboot_common.c

@@ -16,6 +16,7 @@
 #include <boot/coreboot_tables.h>
 #include <boot_device.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/cbmem_console.h>
 #include <console/console.h>
 #include <fmap.h>
@@ -101,7 +102,7 @@ int vboot_handoff_get_recovery_reason(void)
 }
 
 /* ============================ VBOOT REBOOT ============================== */
-void __attribute__((weak)) vboot_platform_prepare_reboot(void)
+void __weak vboot_platform_prepare_reboot(void)
 {
 }
 

src/security/vboot/vboot_logic.c

@@ -17,6 +17,7 @@
 #include <arch/exception.h>
 #include <assert.h>
 #include <bootmode.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <console/vtxprintf.h>
 #include <delay.h>
@@ -95,21 +96,21 @@ int vb2ex_read_resource(struct vb2_context *ctx,
 }
 
 /* No-op stubs that can be overridden by SoCs with hardware crypto support. */
-__attribute__((weak))
+__weak
 int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
 			       uint32_t data_size)
 {
 	return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
 }
 
-__attribute__((weak))
+__weak
 int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
 {
 	BUG();	/* Should never get called if init() returned an error. */
 	return VB2_ERROR_UNKNOWN;
 }
 
-__attribute__((weak))
+__weak
 int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size)
 {
 	BUG();	/* Should never get called if init() returned an error. */

src/security/vboot/verstage.c

@@ -15,11 +15,12 @@
 
 #include <arch/exception.h>
 #include <arch/hlt.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <program_loading.h>
 #include <security/vboot/vboot_common.h>
 
-void __attribute__((weak)) verstage_mainboard_init(void)
+void __weak verstage_mainboard_init(void)
 {
 	/* Default empty implementation. */
 }

src/soc/amd/common/block/pi/agesawrapper.c

@@ -18,6 +18,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <delay.h>
 #include <rules.h>
 #include <rmodule.h>
@@ -28,8 +29,8 @@
 #include <amdblocks/BiosCallOuts.h>
 #include <soc/southbridge.h>
 
-void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {}
-void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {}
+void __weak SetMemParams(AMD_POST_PARAMS *PostParams) {}
+void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {}
 
 /* ACPI table pointers returned by AmdInitLate */
 static void *DmiTable;

src/soc/amd/common/block/pi/def_callouts.c

@@ -15,6 +15,7 @@
  */
 
 #include <cbfs.h>
+#include <compiler.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <timer.h>
@@ -155,7 +156,7 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData,
 	return pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING;
 }
 
-AGESA_STATUS __attribute__((weak)) platform_PcieSlotResetControl(UINT32 Func,
+AGESA_STATUS __weak platform_PcieSlotResetControl(UINT32 Func,
 	UINTN Data, VOID *ConfigPtr)
 {
 	printk(BIOS_WARNING, "Warning - AGESA callout: %s not supported\n",

src/soc/amd/stoneyridge/BiosCallOuts.c

@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <amdblocks/BiosCallOuts.h>
@@ -28,7 +29,7 @@
 #include "chip.h"
 #include <amdblocks/car.h>
 
-void __attribute__((weak)) platform_FchParams_reset(
+void __weak platform_FchParams_reset(
 				FCH_RESET_DATA_BLOCK *FchParams_reset) {}
 
 AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
@@ -159,7 +160,7 @@ AGESA_STATUS agesa_HaltThisAp(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 }
 
 /* Allow mainboards to fill the SPD buffer */
-__attribute__((weak)) int mainboard_read_spd(uint8_t spdAddress, char *buf,
+__weak int mainboard_read_spd(uint8_t spdAddress, char *buf,
 						size_t len)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);

src/soc/amd/stoneyridge/romstage.c

@@ -17,6 +17,7 @@
 #include <arch/io.h>
 #include <arch/cpu.h>
 #include <arch/acpi.h>
+#include <compiler.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
@@ -34,7 +35,7 @@
 #include <soc/southbridge.h>
 #include <amdblocks/psp.h>
 
-void __attribute__((weak)) mainboard_romstage_entry(int s3_resume)
+void __weak mainboard_romstage_entry(int s3_resume)
 {
 	/* By default, don't do anything */
 }

src/soc/amd/stoneyridge/usb.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -42,13 +43,13 @@ static void set_usb_over_current(struct device *dev)
 	}
 }
 
-int __attribute__((weak)) mainboard_get_xhci_oc_map(uint16_t *map)
+int __weak mainboard_get_xhci_oc_map(uint16_t *map)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 	return -1;
 }
 
-int __attribute__((weak)) mainboard_get_ehci_oc_map(uint16_t *map)
+int __weak mainboard_get_ehci_oc_map(uint16_t *map)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 	return -1;

src/soc/intel/apollolake/chip.c

@@ -20,6 +20,7 @@
 #include <arch/acpi.h>
 #include <bootstate.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
@@ -518,7 +519,7 @@ static void glk_fsp_silicon_init_params_cb(
 		sizeof(silconfig->PcieRpSelectableDeemphasis));
 }
 
-void __attribute__((weak)) mainboard_devtree_update(struct device *dev)
+void __weak mainboard_devtree_update(struct device *dev)
 {
        /* Override dev tree settings per board */
 }

src/soc/intel/apollolake/romstage.c

@@ -24,6 +24,7 @@
 #include <bootmode.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <device/pci_def.h>
@@ -370,13 +371,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	car_set_var(fsp_version, version);
 }
 
-__attribute__((weak))
+__weak
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
 
-__attribute__((weak))
+__weak
 void mainboard_save_dimm_info(void)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);

src/soc/intel/baytrail/gpio.c

@@ -14,6 +14,7 @@
  */
 
 #include <device/pci.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <soc/gpio.h>
 #include <soc/pmc.h>
@@ -234,7 +235,7 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
 	}
 }
 
-struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)
+struct soc_gpio_config* __weak mainboard_get_gpios(void)
 {
 	printk(BIOS_DEBUG, "Default/empty GPIO config\n");
 	return NULL;

src/soc/intel/baytrail/southcluster.c

@@ -19,6 +19,7 @@
 #include <arch/acpi.h>
 #include <bootstate.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <device/device.h>
@@ -536,7 +537,7 @@ static const struct pci_driver southcluster __pci_driver = {
 	.device		= LPC_DEVID,
 };
 
-int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg)
+int __weak mainboard_get_spi_config(struct spi_config *cfg)
 {
 	return -1;
 }

src/soc/intel/braswell/acpi.c

@@ -22,6 +22,7 @@
 #include <arch/smp/mpspec.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <compiler.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/turbo.h>
@@ -552,6 +553,6 @@ void southcluster_inject_dsdt(device_t device)
 	}
 }
 
-__attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
+__weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
 {
 }