From 640b040f6f204f39a5f710fa019ab9077674826c Mon Sep 17 00:00:00 2001
From: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Date: Fri, 14 Oct 2022 12:28:02 -0700
Subject: [PATCH] soc/intel/meteorlake: Implement SOC Die lock down
 configuration

This patch implements a function to enable IOSF Primary Trunk Clock
Gating.

BUG=b:253210291
TEST=Able to build and boot rex to OS. Also needed for S0ix, tested
with Sandbox OS + Firmware combination for S0ix entry/exit.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/lockdown.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/soc/intel/meteorlake/lockdown.c b/src/soc/intel/meteorlake/lockdown.c
index 678e63a15c..51fbdaf7fa 100644
--- a/src/soc/intel/meteorlake/lockdown.c
+++ b/src/soc/intel/meteorlake/lockdown.c
@@ -2,10 +2,16 @@
 
 #include <device/mmio.h>
 #include <intelblocks/cfg.h>
+#include <intelblocks/pcr.h>
 #include <intelpch/lockdown.h>
+#include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <stdint.h>
 
+/* PCR PSTH Control Register */
+#define PCR_PSTH_CTRLREG	0x1d00
+#define PSTH_CTRLREG_IOSFPTCGE	(1 << 2)
+
 static void pmc_lock_pmsync(void)
 {
 	uint8_t *pmcbase;
@@ -53,8 +59,19 @@ static void pmc_lockdown_cfg(int chipset_lockdown)
 		pmc_lock_smi();
 }
 
+static void soc_die_lockdown_cfg(void)
+{
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
+		return;
+
+	/* Enable IOSF Primary Trunk Clock Gating */
+	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
+}
+
 void soc_lockdown_config(int chipset_lockdown)
 {
 	/* PMC lock down configuration */
 	pmc_lockdown_cfg(chipset_lockdown);
+	/* SOC Die lock down configuration */
+	soc_die_lockdown_cfg();
 }