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speedstep: Deduplicate some MSR identifiers

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In particular:
MSR_PMG_CST_CONFIG_CONTROL
MSR_PMG_IO_BASE_ADDR
MSR_PMG_IO_CAPTURE_ADDR

Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2337
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi
2013-02-09 15:35:30 +01:00
committed by Stefan Reinauer
parent dbc6ca7aea
commit 644e83b007
8 changed files with 24 additions and 37 deletions
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12
src/cpu/intel/model_106cx/model_106cx_init.c
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@ -80,34 +80,30 @@ static void enable_vmx(void)
wrmsr(IA32_FEATURE_CONTROL, msr);
}
#define PMG_CST_CONFIG_CONTROL 0xe2
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{
msr_t msr;
msr = rdmsr(PMG_CST_CONFIG_CONTROL);
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // Lock configuration
msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
wrmsr(PMG_CST_CONFIG_CONTROL, msr);
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;
// TODO Do we want PM1_BASE? Needs SMM?
//msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
msr.lo = ((PMB0_BASE + 4) & 0xffff);
wrmsr(PMG_IO_BASE_ADDR, msr);
wrmsr(MSR_PMG_IO_BASE_ADDR, msr);
/* set C_LVL controls */
msr.hi = 0;
msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
wrmsr(PMG_IO_CAPTURE_ADDR, msr);
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}
#define IA32_MISC_ENABLE 0x1a0