soc/mainboard: Update mainboard UART Kconfig

After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/mainboard/intel/kunimitsu/Kconfig

@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
+	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_LPC_TPM
 	select SOC_INTEL_SKYLAKE
@@ -72,4 +73,8 @@ config GBB_HWID
 	string
 	depends on CHROMEOS
 	default "KUNIMITSU TEST 8819"
+
+config UART_FOR_CONSOLE
+	int
+	default 2
 endif