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amd/geode_lx: Remove most boards

Browse Source 
There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.

Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2018-06-04 06:49:00 +03:00
parent 88af0f38eb
commit 64aa881263
124 changed files with 0 additions and 5844 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
src/mainboard/iei/pcisa-lx-800-r10/Kconfig
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if BOARD_IEI_PCISA_LX_800_R10
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
default iei/pcisa-lx-800-r10
config MAINBOARD_PART_NUMBER
string
default "PCISA-LX-800-R10"
config IRQ_SLOT_COUNT
int
default 9
config PLLMSRlo
hex
default 0x00DE6000
endif # BOARD_IEI_PCISA_LX_800_R10

2
src/mainboard/iei/pcisa-lx-800-r10/Kconfig.name
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config BOARD_IEI_PCISA_LX_800_R10
bool "PCISA LX-800-R10"

2
src/mainboard/iei/pcisa-lx-800-r10/board_info.txt
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@@ -1,2 +0,0 @@
Category: half
Board URL: http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX

75
src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
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@@ -1,75 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x0000105a"
register "lpc_serirq_polarity" = "0x0000EFA5"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "1" # 0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 9.0 on end # Slot1
device pci a.0 on end # Slot2
device pci b.0 on end # Slot3
device pci c.0 on end # Slot4
device pci e.0 on end # Ethernet 0
device pci 10.0 on end # Ethernet 1
device pci 11.0 on end # SATA
device pci f.0 on # ISA Bridge
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b off end # HW Monitor
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

292
src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c
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@@ -1,292 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
// #include <console/console.h>
#include <arch/io.h>
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 10
#define PIRQC 11
#define PIRQD 5
/* Link */
#define LINK_PIRQA 1
#define LINK_PIRQB 2
#define LINK_PIRQC 3
#define LINK_PIRQD 4
#define LINK_NONE 0
/* Map */
#define IRQ_BITMAP_LINKA (1 << PIRQA)
#define IRQ_BITMAP_LINKB (1 << PIRQB)
#define IRQ_BITMAP_LINKC (1 << PIRQC)
#define IRQ_BITMAP_LINKD (1 << PIRQD)
#define IRQ_BITMAP_NOLINK 0x0
#define EXCLUSIVE_PCI_IRQS (IRQ_BITMAP_LINKA | IRQ_BITMAP_LINKB | IRQ_BITMAP_LINKC | IRQ_BITMAP_LINKD)
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */
0x1078, /* Vendor */
0x0002, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x62, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
.slots = {
[0] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x01 << 3)|0x0, /* 0x01 is CS5536 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[1] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x0f << 3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQB, /* Audio */
.bitmap = IRQ_BITMAP_LINKB
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQD, /* USB */
.bitmap = IRQ_BITMAP_LINKD
}
}
},
[2] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x0e << 3)|0x0, /* 0x0e is eth0 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[3] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x10 << 3)|0x0, /* 0x10 is eth1 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[4] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x11 << 3)|0x0, /* 0x11 is SATA */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
/*
* ################### backplane ###################
*/
/*
* PCI1
*/
[5] = {
.slot = 0x1, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x09 << 3)|0x0, /* 0x09 is PCI1 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
}
}
},
/*
* PCI2
*/
[6] = {
.slot = 0x2, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0a << 3)|0x0, /* 0x0a is PCI2 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
}
}
},
/*
* PCI3
*/
[7] = {
.slot = 0x3, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0b << 3)|0x0, /* 0x0b is PCI3 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
}
}
},
/*
* PCI4
*/
[8] = {
.slot = 0x4, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0c << 3)|0x0, /* 0x0c is PCI4 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
}
}
},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
/* Put the PIR table in memory and checksum. */
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

73
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
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@@ -1,73 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <spd.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
}

48
src/mainboard/iei/pm-lx-800-r11/Kconfig
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@@ -1,48 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_IEI_PM_LX_800_R11
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627EHG
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
default iei/pm-lx-800-r11
config MAINBOARD_PART_NUMBER
string
default "PM-LX-800-R11"
config IRQ_SLOT_COUNT
int
default 7
config PLLMSRlo
hex
default 0x07de0000
endif # BOARD_IEI_PM_LX_800_R11

2
src/mainboard/iei/pm-lx-800-r11/Kconfig.name
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@@ -1,2 +0,0 @@
config BOARD_IEI_PM_LX_800_R11
bool "PM LX-800-R11"

6
src/mainboard/iei/pm-lx-800-r11/board_info.txt
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@@ -1,6 +0,0 @@
Category: half
Board URL: http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110#.UCLx8cLlgao
ROM package: PLCC
ROM protocol: LPC
ROM socketed: y
Flashrom support: y

96
src/mainboard/iei/pm-lx-800-r11/devicetree.cb
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@@ -1,96 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Video Adapter
device pci 1.2 on end # AES Security Block
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x0000115a"
register "lpc_serirq_polarity" = "0x0000eea5"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0d0c0700"
register "enable_ide_nand_flash" = "0"
register "enable_USBP4_device" = "0" # 0:host, 1:device
register "enable_USBP4_overcurrent" = "0"
register "com1_enable" = "1" # CN10 (RS422/486 COM3)
register "com1_address" = "0x3e8"
register "com1_irq" = "5"
register "com2_enable" = "0"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci e.0 on end # RTL8100C
device pci f.0 on # ISA Bridge
chip superio/winbond/w83627ehg # Winbond W83627EHG
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 keyboard/mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # Keyboard
irq 0x72 = 12 # Mouse
end
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 0
end
device pnp 2e.6 off end # Serial Flash Interface
device pnp 2e.7 off end # GPIO1, GPIO6, Game Port & MIDI Port
device pnp 2e.8 off end # WDTO# & PLED
device pnp 2e.9 off end # GPIO2,GPIO3, GPIO4, GPIO5 & SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.106 off end #
device pnp 2e.107 off end #
device pnp 2e.207 off end #
end
end
device pci f.2 on end # IDE Controller
device pci f.3 off end # Audio (N/A)
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

224
src/mainboard/iei/pm-lx-800-r11/irq_tables.c
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@@ -1,224 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ids.h>
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 11
#define PIRQC 11
#define PIRQD 11
/* Links */
#define L_PIRQA 1
#define L_PIRQB 2
#define L_PIRQC 3
#define L_PIRQD 4
/* Bitmaps */
#define B_LINK0 (1 << PIRQA)
#define B_LINK1 (1 << PIRQB)
#define B_LINK2 (1 << PIRQC)
#define B_LINK3 (1 << PIRQD)
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
0x0f << 3, /* Interrupt router dev */
B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3, /* IRQs devoted exclusively to PCI usage */
PCI_VENDOR_ID_AMD, /* Vendor */
PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */
0, /* Miniport */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* Reserved */
0xa6, /* Checksum */
{
[0] = { /* Host bridge */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x01 << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[1] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[2] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[3] = {
.link = L_PIRQD,
.bitmap = B_LINK3
}
}
},
[1] = { /* ISA bridge */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x0f << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[1] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[2] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[3] = {
.link = L_PIRQD,
.bitmap = B_LINK3
}
}
},
[2] = { /* Ethernet */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x0e << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[1] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[2] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[3] = {
.link = L_PIRQC,
.bitmap = B_LINK2
}
}
},
[3] = { /* PCI Connector - Slot 0 */
.slot = 0x01,
.bus = 0x00,
.devfn = (0x09 << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[1] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[2] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[3] = {
.link = L_PIRQD,
.bitmap = B_LINK3
}
}
},
[4] = { /* PCI Connector - Slot 1 */
.slot = 0x02,
.bus = 0x00,
.devfn = (0x0c << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[1] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[2] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[3] = {
.link = L_PIRQA,
.bitmap = B_LINK0
}
}
},
[5] = { /* PCI Connector - Slot 2 */
.slot = 0x03,
.bus = 0x00,
.devfn = (0x0b << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[1] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[2] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[3] = {
.link = L_PIRQB,
.bitmap = B_LINK1
}
}
},
[6] = { /* PCI Connector - Slot 3 */
.slot = 0x04,
.bus = 0x00,
.devfn = (0x0a << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[1] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[2] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[3] = {
.link = L_PIRQC,
.bitmap = B_LINK2
}
}
}
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

69
src/mainboard/iei/pm-lx-800-r11/romstage.c
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@@ -1,69 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdlib.h>
#include <spd.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
/* Only DIMM0 is available. */
if (device != DIMM0)
return 0xff;
return smbus_read_byte(device, address);
}
#include <northbridge/amd/lx/pll_reset.c>
#include <cpu/amd/geode_lx/cpureginit.c>
#include <cpu/amd/geode_lx/syspreinit.c>
#include <cpu/amd/geode_lx/msrinit.c>
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
}

48
src/mainboard/iei/pm-lx2-800-r10/Kconfig
View File

@@ -1,48 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_IEI_PM_LX2_800_R10
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
default iei/pm-lx2-800-r10
config MAINBOARD_PART_NUMBER
string
default "PM-LX2-800-R10"
config IRQ_SLOT_COUNT
int
default 3
config PLLMSRlo
hex
default 0x07de0000
endif # BOARD_IEI_PM_LX2_800_R10

2
src/mainboard/iei/pm-lx2-800-r10/Kconfig.name
View File

@@ -1,2 +0,0 @@
config BOARD_IEI_PM_LX2_800_R10
bool "PM LX2-800-R10"

6
src/mainboard/iei/pm-lx2-800-r10/board_info.txt
View File

@@ -1,6 +0,0 @@
Category: half
Board URL: http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=09034367569861123956#.UI2CfiExUao
ROM package: PLCC
ROM protocol: LPC
ROM socketed: y
Flashrom support: y

82
src/mainboard/iei/pm-lx2-800-r10/devicetree.cb
View File

@@ -1,82 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Video Adapter
device pci 1.2 on end # AES Security Block
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x000010da"
register "lpc_serirq_polarity" = "0x0000ef25"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0d0c0700"
register "enable_ide_nand_flash" = "0"
register "enable_USBP4_device" = "0" # 0:host, 1:device
register "enable_USBP4_overcurrent" = "0"
register "com1_enable" = "0"
register "com2_enable" = "0"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 11.0 on end # IT8888
device pci e.0 on end # RTL8100C
device pci f.0 on # ISA Bridge
chip superio/smsc/smscsuperio # SMSC SCH3114
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.7 on # PS/2 keyboard/mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # Keyboard
irq 0x72 = 12 # Mouse
end
device pnp 2e.a on # Runtime Register
io 0x60 = 0x400
end
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

130
src/mainboard/iei/pm-lx2-800-r10/irq_tables.c
View File

@@ -1,130 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ids.h>
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 10
#define PIRQC 11
#define PIRQD 11
/* Links */
#define L_PIRQN 0
#define L_PIRQA 1
#define L_PIRQB 2
#define L_PIRQC 3
#define L_PIRQD 4
/* Bitmaps */
#define B_LINKN (0)
#define B_LINK0 (1 << PIRQA)
#define B_LINK1 (1 << PIRQB)
#define B_LINK2 (1 << PIRQC)
#define B_LINK3 (1 << PIRQD)
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x0f << 3) | 0x0, /* Interrupt router dev */
(B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */
PCI_VENDOR_ID_AMD, /* Vendor */
PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */
0, /* Miniport */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
0x27, /* Checksum */
{
[0] = { /* Host bridge */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x01 << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[1] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[2] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[3] = {
.link = L_PIRQN,
.bitmap = B_LINKN
}
}
},
[1] = { /* ISA bridge */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x0f << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[1] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[2] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[3] = {
.link = L_PIRQD,
.bitmap = B_LINK3
}
}
},
[2] = { /* Ethernet */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x0e << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[1] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[2] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[3] = {
.link = L_PIRQN,
.bitmap = B_LINKN
}
}
}
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

47
src/mainboard/iei/pm-lx2-800-r10/mainboard.c
View File

@@ -1,47 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/device.h>
#include <boot/tables.h>
/* SCH3114 runtime register (RTR) address. */
#define SCH3114_RTR_ADDR (0x400)
/* H/W Monitoring register block index. */
#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70)
/* H/W Monitoring register block data. */
#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71)
/* H/W Monitoring Ready/Lock/Start register. */
#define SCH3114_HWM_RLS_REG (0x40)
static void init(struct device *dev)
{
/* SCH3114: enable hardware monitor. */
printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n");
outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX);
outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

81
src/mainboard/iei/pm-lx2-800-r10/romstage.c
View File

@@ -1,81 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <spd.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
/* Only DIMM0 is available. */
if (device != DIMM0)
return 0xFF;
return smbus_read_byte(device, address);
}
#include <northbridge/amd/lx/pll_reset.c>
#include <cpu/amd/geode_lx/cpureginit.c>
#include <cpu/amd/geode_lx/syspreinit.c>
#include <cpu/amd/geode_lx/msrinit.c>
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Enable COM3. */
pnp_devfn_t dev = PNP_DEV(0x2e, 0x0b);
u16 port = dev >> 8;
outb(0x55, port);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1);
outb(0xaa, port);
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
}