soc/amd: Add an option to select if SOC supports ESPI sub decode

Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.

Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Zheng Bao
2020-12-21 13:56:22 +08:00
committed by Felix Held
parent 56868b8045
commit 64d0ad347b
3 changed files with 8 additions and 1 deletions

View File

@@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
select SOC_AMD_COMMON_BLOCK_HAS_ESPI_SUB_DECODE
select SOC_AMD_COMMON_BLOCK_IOMMU
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS