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soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms

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NUMA will be supported by SPR and future generations.

TEST=intel/archercity CRB

Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Shuo Liu 2023-03-29 20:14:11 +08:00 committed by Lean Sheng Tan
parent 04fde7ed37
commit 64d2fd0777
5 changed files with 6 additions and 5 deletions
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3
src/soc/intel/xeon_sp/Kconfig
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@ -106,4 +106,7 @@ config SOC_INTEL_XEON_RAS
config HAVE_IOAT_DOMAINS config HAVE_IOAT_DOMAINS
bool bool
config SOC_INTEL_HAS_CXL
bool
endif ## SOC_INTEL_XEON_SP endif ## SOC_INTEL_XEON_SP

2
src/soc/intel/xeon_sp/Makefile.mk
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@ -13,7 +13,7 @@ ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c
ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-y += memmap.c pch.c lockdown.c finalize.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c
ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
smm-y += smihandler.c pmutil.c smm-y += smihandler.c pmutil.c
postcar-y += spi.c postcar-y += spi.c

0
src/soc/intel/xeon_sp/spr/numa.c → src/soc/intel/xeon_sp/numa.c
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4
src/soc/intel/xeon_sp/spr/Kconfig
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@ -15,6 +15,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP
select HAVE_IOAT_DOMAINS select HAVE_IOAT_DOMAINS
select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
select UDK_202005_BINDING select UDK_202005_BINDING
select SOC_INTEL_HAS_CXL
help help
Intel Sapphire Rapids-SP support Intel Sapphire Rapids-SP support
@ -114,9 +115,6 @@ config SOC_INTEL_HAS_BIOS_DONE_MSR
config SOC_INTEL_HAS_NCMEM config SOC_INTEL_HAS_NCMEM
def_bool y def_bool y
config SOC_INTEL_HAS_CXL
def_bool y
config SOC_INTEL_PCIE_64BIT_ALLOC config SOC_INTEL_PCIE_64BIT_ALLOC
def_bool y def_bool y

2
src/soc/intel/xeon_sp/spr/Makefile.mk
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@ -12,7 +12,7 @@ romstage-y += romstage.c soc_util.c ddr.c
romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c numa.c reset.c ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c
ramstage-y += crashlog.c ioat.c ramstage-y += crashlog.c ioat.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c