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arch/riscv: Remove supervisor_trap_entry

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coreboot only maintains a single trap entry, because it only runs in
machine mode.

Change-Id: I7324d9c8897d5c4e9d4784e7bc2a055890eab698
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer
2017-09-29 01:37:00 +02:00
committed by Martin Roth
parent c0c31b6d1a
commit 64d855dbb0
1 changed files with 1 additions and 9 deletions
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10
src/arch/riscv/trap_util.S
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@@ -107,15 +107,7 @@
.globl estack .globl estack
.text .text
.global supervisor_trap_entry
supervisor_trap_entry:
csrw mscratch, sp
# load in the top of the machine stack
la sp, _estack
addi sp,sp,-MENTRY_FRAME_SIZE
save_tf
move a0,sp
jal trap_handler
.global trap_entry .global trap_entry
trap_entry: trap_entry:
csrw mscratch, sp csrw mscratch, sp