security/tpm: Move tpm TSS and TSPI layer to security section

* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes

Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/Kconfig

@@ -291,14 +291,6 @@ config FMDFILE
 	  but in some cases more complex setups are required.
 	  When an fmd is specified, it overrides the default format.
 
-config MAINBOARD_HAS_TPM2
-	bool
-	default n
-	help
-	  There is a TPM device installed on the mainboard, and it is
-	  compliant with version 2 TCG TPM specification. Could be connected
-	  over LPC, SPI or I2C.
-
 endmenu
 
 # load site-local kconfig to allow user specific defaults and overrides
@@ -387,37 +379,6 @@ config RTC
 	bool
 	default n
 
-config TPM
-	bool
-	default n
-	select LPC_TPM if MAINBOARD_HAS_LPC_TPM
-	select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
-	help
-	  Enable this option to enable TPM support in coreboot.
-
-	  If unsure, say N.
-
-config TPM2
-	bool
-	select LPC_TPM if MAINBOARD_HAS_LPC_TPM
-	select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
-	help
-	  Enable this option to enable TPM2 support in coreboot.
-
-	  If unsure, say N.
-
-config POWER_OFF_ON_CR50_UPDATE
-	bool
-	help
-	  Power off machine while waiting for CR50 update to take effect.
-
-config MAINBOARD_HAS_TPM_CR50
-	bool
-	default y if MAINBOARD_HAS_SPI_TPM_CR50 || MAINBOARD_HAS_I2C_TPM_CR50
-	default n
-	select MAINBOARD_HAS_TPM2
-	select POWER_OFF_ON_CR50_UPDATE if ARCH_X86
-
 config HEAP_SIZE
 	hex
 	default 0x4000
@@ -962,13 +923,6 @@ config X86EMU_DEBUG_TIMINGS
 
 	  If unsure, say N.
 
-config DEBUG_TPM
-	bool "Output verbose TPM debug messages"
-	default n
-	depends on TPM || TPM2
-	help
-	  This option enables additional TPM related debug messages.
-
 config DEBUG_SPI_FLASH
 	bool "Output verbose SPI flash debug messages"
 	default n

src/cpu/intel/haswell/romstage.c

@@ -42,7 +42,7 @@
 #include "northbridge/intel/haswell/raminit.h"
 #include "southbridge/intel/lynxpoint/pch.h"
 #include "southbridge/intel/lynxpoint/me.h"
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 static inline void reset_system(void)
 {

src/drivers/i2c/tpm/cr50.c

@@ -39,7 +39,7 @@
 #include <device/i2c_simple.h>
 #include <endian.h>
 #include <timer.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include "tpm.h"
 
 #define CR50_MAX_BUFSIZE	63

src/drivers/i2c/tpm/tis.c

@@ -22,7 +22,7 @@
 #include <device/i2c_simple.h>
 #include <endian.h>
 #include <lib.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include "tpm.h"
 #include <timer.h>
 

src/drivers/i2c/tpm/tis_atmel.c

@@ -23,7 +23,7 @@
 #include <device/i2c_simple.h>
 #include <endian.h>
 #include <lib.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <timer.h>
 
 #define RECV_TIMEOUT            (1 * 1000)  /* 1 second */

src/drivers/i2c/tpm/tpm.c

@@ -38,7 +38,7 @@
 #include <device/i2c_simple.h>
 #include <endian.h>
 #include <timer.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include "tpm.h"
 
 /* max. number of iterations after I2C NAK */

src/drivers/intel/fsp1_1/romstage.c

@@ -36,7 +36,7 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)

src/drivers/intel/fsp2_0/memory_init.c

@@ -12,7 +12,7 @@
  */
 
 #include <compiler.h>
-#include <antirollback.h>
+#include <security/tpm/antirollback.h>
 #include <arch/io.h>
 #include <arch/cpu.h>
 #include <arch/symbols.h>
@@ -31,7 +31,7 @@
 #include <string.h>
 #include <symbols.h>
 #include <timestamp.h>
-#include <tpm_lite/tlcl.h>
+#include <security/tpm/tlcl.h>
 #include <security/vboot/vboot_common.h>
 #include <vb2_api.h>
 

src/drivers/pc80/tpm/Kconfig

@@ -1,9 +1,3 @@
-config MAINBOARD_HAS_LPC_TPM
-	bool
-	default n
-	help
-	  Board has TPM support
-
 config LPC_TPM
 	bool "Enable TPM support"
 	depends on MAINBOARD_HAS_LPC_TPM

src/drivers/pc80/tpm/romstage.c

@@ -17,7 +17,7 @@
 #include <console/cbmem_console.h>
 #include <console/console.h>
 #include <arch/acpi.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <reset.h>
 
 //#define EXTRA_LOGGING

src/drivers/pc80/tpm/tpm.c

@@ -32,7 +32,7 @@
 #include <arch/acpi_device.h>
 #include <device/device.h>
 #include <console/console.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <arch/early_variables.h>
 #include <device/pnp.h>
 #include "chip.h"

src/drivers/spi/tpm/tis.c

@@ -7,7 +7,7 @@
 #include <arch/early_variables.h>
 #include <console/console.h>
 #include <string.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 #include "tpm.h"
 

src/drivers/spi/tpm/tpm.c

@@ -23,7 +23,7 @@
 #include <endian.h>
 #include <string.h>
 #include <timer.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 #include "tpm.h"
 

src/lib/Makefile.inc

@@ -53,16 +53,6 @@ verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 verstage-y += boot_device.c
 verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 
-verstage-$(CONFIG_TPM) += tlcl.c
-verstage-$(CONFIG_TPM2) += tpm2_marshaling.c
-verstage-$(CONFIG_TPM2) += tpm2_tlcl.c
-
-ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y)
-romstage-$(CONFIG_TPM) += tlcl.c
-romstage-$(CONFIG_TPM2) += tpm2_marshaling.c
-romstage-$(CONFIG_TPM2) += tpm2_tlcl.c
-endif # CONFIG_VBOOT_SEPARATE_VERSTAGE
-
 verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
 
@@ -144,8 +134,6 @@ ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
 ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 ramstage-y += b64_decode.c
 ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c
-ramstage-$(CONFIG_TPM2) += tpm2_marshaling.c
-ramstage-$(CONFIG_TPM2) += tpm2_tlcl.c
 
 romstage-y += cbmem_common.c
 romstage-y += imd_cbmem.c

src/mainboard/asus/kgpe-d16/romstage.c

@@ -46,7 +46,7 @@
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
 #include <arch/early_variables.h>
 #include <cbmem.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"

src/mainboard/google/gru/chromeos.c

@@ -17,7 +17,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 #include "board.h"
 

src/mainboard/google/link/romstage.c

@@ -35,7 +35,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <cbfs.h>
 
 #include <southbridge/intel/bd82x6x/chip.h>

src/mainboard/google/oak/tpm_tis.c

@@ -14,7 +14,7 @@
  */
 
 #include <gpio.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 #include "gpio.h"
 

src/mainboard/google/parrot/romstage.c

@@ -35,7 +35,7 @@
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <cbfs.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include "ec/compal/ene932/ec.h"
 
 void pch_enable_lpc(void)

src/mainboard/google/stout/romstage.c

@@ -35,7 +35,7 @@
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <bootmode.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <cbfs.h>
 #include <ec/quanta/it8518/ec.h>
 #include "ec.h"

src/mainboard/intel/emeraldlake2/romstage.c

@@ -35,7 +35,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 #define SIO_PORT 0x164e
 

src/mainboard/lenovo/x201/romstage.c

@@ -35,7 +35,7 @@
 #include <timestamp.h>
 #include <arch/acpi.h>
 #include <cbmem.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 #include "dock.h"
 #include "arch/early_variables.h"

src/mainboard/pcengines/apu2/romstage.c

@@ -33,7 +33,7 @@
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <Fch/Fch.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 #include "gpio_ftns.h"
 

src/mainboard/samsung/lumpy/romstage.c

@@ -28,7 +28,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <bootmode.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>

src/mainboard/samsung/stumpy/romstage.c

@@ -37,7 +37,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif

src/northbridge/intel/sandybridge/romstage.c

@@ -28,7 +28,7 @@
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <halt.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <northbridge/intel/sandybridge/chip.h>
 #include "southbridge/intel/bd82x6x/pch.h"
 #include <southbridge/intel/common/gpio.h>

src/security/Kconfig

@@ -13,3 +13,4 @@
 ##
 
 source "src/security/vboot/Kconfig"
+source "src/security/tpm/Kconfig"

src/security/Makefile.inc

@@ -1 +1,2 @@
 subdirs-y += vboot
+subdirs-y += tpm

src/security/tpm/Kconfig

@@ -0,0 +1,69 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Philipp Deppenwiese, Facebook, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+menu "Trusted Platform Module"
+
+config TPM
+	bool
+	default n
+	select LPC_TPM if MAINBOARD_HAS_LPC_TPM
+	select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
+	help
+	  Enable this option to enable TPM support in coreboot.
+
+	  If unsure, say N.
+
+config TPM2
+	bool
+	select LPC_TPM if MAINBOARD_HAS_LPC_TPM
+	select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
+	help
+	  Enable this option to enable TPM2 support in coreboot.
+
+	  If unsure, say N.
+
+config DEBUG_TPM
+	bool "Output verbose TPM debug messages"
+	default n
+	depends on TPM || TPM2
+	help
+	  This option enables additional TPM related debug messages.
+
+config MAINBOARD_HAS_TPM_CR50
+	bool
+	default y if MAINBOARD_HAS_SPI_TPM_CR50 || MAINBOARD_HAS_I2C_TPM_CR50
+	default n
+	select MAINBOARD_HAS_TPM2
+	select POWER_OFF_ON_CR50_UPDATE if ARCH_X86
+
+config POWER_OFF_ON_CR50_UPDATE
+	bool
+	help
+	  Power off machine while waiting for CR50 update to take effect.
+
+config MAINBOARD_HAS_LPC_TPM
+	bool
+	default n
+	help
+	  Board has TPM support
+
+config MAINBOARD_HAS_TPM2
+	bool
+	default n
+	help
+	  There is a TPM device installed on the mainboard, and it is
+	  compliant with version 2 TCG TPM specification. Could be connected
+	  over LPC, SPI or I2C.
+
+endmenu # Trusted Platform Module (tpm)

src/security/tpm/Makefile.inc

@@ -0,0 +1,12 @@
+verstage-$(CONFIG_TPM) += tcg-1.2/tlcl.c
+verstage-$(CONFIG_TPM2) += tcg-2.0/tpm2_marshaling.c
+verstage-$(CONFIG_TPM2) += tcg-2.0/tpm2_tlcl.c
+
+ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y)
+romstage-$(CONFIG_TPM) += tcg-1.2/tlcl.c
+romstage-$(CONFIG_TPM2) += tcg-2.0/tpm2_marshaling.c
+romstage-$(CONFIG_TPM2) += tcg-2.0/tpm2_tlcl.c
+endif # CONFIG_VBOOT_SEPARATE_VERSTAGE
+
+ramstage-$(CONFIG_TPM2) += tcg-2.0/tpm2_marshaling.c
+ramstage-$(CONFIG_TPM2) += tcg-2.0/tpm2_tlcl.c

src/security/tpm/antirollback.h

@@ -9,7 +9,7 @@
 #ifndef ANTIROLLBACK_H_
 #define ANTIROLLBACK_H_
 
-#include "tpm_lite/tss_constants.h"
+#include "tss_constants.h"
 
 struct vb2_context;
 enum vb2_pcr_digest;

src/security/tpm/tcg-1.2/tlcl.c

@@ -17,11 +17,11 @@
 #include <arch/early_variables.h>
 #include <assert.h>
 #include <string.h>
-#include <tpm_lite/tlcl.h>
+#include <security/tpm/tpm.h>
-#include <tpm.h>
 #include <vb2_api.h>
 #include "tlcl_internal.h"
 #include "tlcl_structures.h"
+#include "../tlcl.h"
 
 #ifdef FOR_TEST
 #include <stdio.h>

src/security/tpm/tcg-2.0/tpm2_tlcl.c

@@ -4,16 +4,16 @@
  * found in the LICENSE file.
  */
 
-#include <antirollback.h>
 #include <arch/early_variables.h>
 #include <console/console.h>
 #include <endian.h>
-#include <lib/tpm2_tlcl_structures.h>
 #include <string.h>
-#include <tpm.h>
 #include <vb2_api.h>
 
+#include "tpm2_tlcl_structures.h"
 #include "tpm2_marshaling.h"
+#include "../tpm.h"
+#include "../antirollback.h"
 
 /*
  * This file provides interface between firmware and TPM2 device. The TPM1.2

src/security/tpm/tcg-2.0/tpm2_tlcl_structures.h

@@ -13,9 +13,10 @@
  */
 #include <stdint.h>
 #include <compiler.h>
-#include <tpm_lite/tlcl.h>
 #include <types.h>
 
+#include "../tlcl.h"
+
 /* This should be plenty for what firmware needs. */
 #define TPM_BUFFER_SIZE 256
 

src/security/vboot/secdata_mock.c

@@ -32,9 +32,9 @@
  * stored in the TPM NVRAM.
  */
 
-#include <antirollback.h>
+#include <security/tpm/antirollback.h>
 #include <stdlib.h>
-#include <tpm_lite/tlcl.h>
+#include <security/tpm/tlcl.h>
 #include <vb2_api.h>
 
 uint32_t tpm_extend_pcr(struct vb2_context *ctx, int pcr,

src/security/vboot/secdata_tpm.c

@@ -32,10 +32,10 @@
  * stored in the TPM NVRAM.
  */
 
-#include <antirollback.h>
+#include <security/tpm/antirollback.h>
 #include <stdlib.h>
 #include <string.h>
-#include <tpm_lite/tlcl.h>
+#include <security/tpm/tlcl.h>
 #include <vb2_api.h>
 #include <console/console.h>
 

src/security/vboot/vboot_logic.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <antirollback.h>
+#include <security/tpm/antirollback.h>
 #include <arch/exception.h>
 #include <assert.h>
 #include <bootmode.h>

src/soc/intel/baytrail/romstage/romstage.c

@@ -30,7 +30,7 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>

src/soc/intel/braswell/romstage/romstage.c

@@ -43,7 +43,7 @@
 #include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/spi.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 void program_base_addresses(void)
 {

src/soc/intel/broadwell/romstage/romstage.c

@@ -25,7 +25,7 @@
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #include <elog.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <stage_cache.h>

src/soc/intel/common/tpm_tis.c

@@ -14,7 +14,7 @@
  */
 
 #include <arch/acpi.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
 
 int tis_plat_irq_status(void)
 {

src/vendorcode/google/chromeos/cr50_enable_update.c

@@ -18,7 +18,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <elog.h>
 #include <halt.h>
-#include <tpm_lite/tlcl.h>
+#include <security/tpm/tlcl.h>
 #include <vb2_api.h>
 #include <security/vboot/vboot_common.h>
 
@@ -71,4 +71,3 @@ static void enable_update(void *unused)
 	halt();
 }
 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, enable_update, NULL);
-

src/vendorcode/google/chromeos/tpm2.c

@@ -15,7 +15,7 @@
 
 #include <bootstate.h>
 #include <console/console.h>
-#include <tpm_lite/tlcl.h>
+#include <security/tpm/tlcl.h>
 #include <vb2_api.h>
 
 static void disable_platform_hierarchy(void *unused)