sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Drop \r\n and \n\r as both print_XXX and printk now do this internally.

Browse Source 
Only some assembler files still have \r\n ... Can we move that part to C
completely?

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-03-31 14:47:43 +00:00
committed by Stefan Reinauer
parent 5a1f597085
commit 64ed2b7345
186 changed files with 1278 additions and 1278 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/console/console.c
View File

@ -100,12 +100,12 @@ void __attribute__((noreturn)) die(const char *msg)
void console_init(void) void console_init(void)
{ {
static const char console_test[] = static const char console_test[] =
"\r\n\r\ncoreboot-" "\n\ncoreboot-"
COREBOOT_VERSION COREBOOT_VERSION
COREBOOT_EXTRA_VERSION COREBOOT_EXTRA_VERSION
" " " "
COREBOOT_BUILD COREBOOT_BUILD
" starting...\r\n"; " starting...\n";
print_info(console_test); print_info(console_test);
} }
@ -115,7 +115,7 @@ void post_code(u8 value)
#if CONFIG_SERIAL_POST==1 #if CONFIG_SERIAL_POST==1
print_emerg("POST: 0x"); print_emerg("POST: 0x");
print_emerg_hex8(value); print_emerg_hex8(value);
print_emerg("\r\n"); print_emerg("\n");
#endif #endif
outb(value, 0x80); outb(value, 0x80);
#endif #endif

10
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -5,7 +5,7 @@
static inline void print_debug_pcar(const char *strval, uint32_t val) static inline void print_debug_pcar(const char *strval, uint32_t val)
{ {
printk(BIOS_DEBUG, "%s%08x\r\n", strval, val); printk(BIOS_DEBUG, "%s%08x\n", strval, val);
} }
/* from linux kernel 2.6.32 asm/string_32.h */ /* from linux kernel 2.6.32 asm/string_32.h */
@ -86,10 +86,10 @@ static void post_cache_as_ram(void)
/* We can put data to stack again */ /* We can put data to stack again */
/* only global variable sysinfo in cache need to be offset */ /* only global variable sysinfo in cache need to be offset */
print_debug("Done\r\n"); print_debug("Done\n");
print_debug_pcar("testx = ", testx); print_debug_pcar("testx = ", testx);
print_debug("Disabling cache as ram now \r\n"); print_debug("Disabling cache as ram now \n");
disable_cache_as_ram_bsp(); disable_cache_as_ram_bsp();
print_debug("Clearing initial memory region: "); print_debug("Clearing initial memory region: ");
@ -99,7 +99,7 @@ static void post_cache_as_ram(void)
#else #else
memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
#endif #endif
print_debug("Done\r\n"); print_debug("Done\n");
// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
@ -115,5 +115,5 @@ static void post_cache_as_ram(void)
copy_and_run(); copy_and_run();
/* We will not return */ /* We will not return */
print_debug("should not be here -\r\n"); print_debug("should not be here -\n");
} }

2
src/cpu/amd/dualcore/amd_sibling.c
View File

@ -109,7 +109,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) { if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID // We need to enable APIC EXT ID
printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n"); printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
enable_apic_ext_id(nodes); enable_apic_ext_id(nodes);
} }

12
src/cpu/amd/model_fxx/fidvid.c
View File

@ -15,21 +15,21 @@
static inline void print_debug_fv(const char *str, unsigned val) static inline void print_debug_fv(const char *str, unsigned val)
{ {
#if K8_SET_FIDVID_DEBUG == 1 #if K8_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x\r\n", str, val); printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif #endif
} }
static inline void print_debug_fv_8(const char *str, unsigned val) static inline void print_debug_fv_8(const char *str, unsigned val)
{ {
#if K8_SET_FIDVID_DEBUG == 1 #if K8_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%02x\r\n", str, val); printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif #endif
} }
static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2) static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
{ {
#if K8_SET_FIDVID_DEBUG == 1 #if K8_SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x%x\r\n", str, val, val2); printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif #endif
} }
@ -131,7 +131,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
apicidx = lapicid(); apicidx = lapicid();
if (apicid != apicidx) { if (apicid != apicidx) {
printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx); printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx);
return fidvid; return fidvid;
} }
@ -328,10 +328,10 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
if (showmessage) { if (showmessage) {
if (vid_new != vid_cur) { if (vid_new != vid_cur) {
print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
} }
if (fid_new != fid_cur) { if (fid_new != fid_cur) {
print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
} }
} }

16
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -16,7 +16,7 @@
static inline void print_initcpu8 (const char *strval, unsigned val) static inline void print_initcpu8 (const char *strval, unsigned val)
{ {
printk(BIOS_DEBUG, "%s%02x\r\n", strval, val); printk(BIOS_DEBUG, "%s%02x\n", strval, val);
} }
static inline void print_initcpu8_nocr (const char *strval, unsigned val) static inline void print_initcpu8_nocr (const char *strval, unsigned val)
@ -27,12 +27,12 @@ static inline void print_initcpu8_nocr (const char *strval, unsigned val)
static inline void print_initcpu16 (const char *strval, unsigned val) static inline void print_initcpu16 (const char *strval, unsigned val)
{ {
printk(BIOS_DEBUG, "%s%04x\r\n", strval, val); printk(BIOS_DEBUG, "%s%04x\n", strval, val);
} }
static inline void print_initcpu(const char *strval, unsigned val) static inline void print_initcpu(const char *strval, unsigned val)
{ {
printk(BIOS_DEBUG, "%s%08x\r\n", strval, val); printk(BIOS_DEBUG, "%s%08x\n", strval, val);
} }
typedef void (*process_ap_t)(unsigned apicid, void *gp); typedef void (*process_ap_t)(unsigned apicid, void *gp);
@ -155,7 +155,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid);
static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str) static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
{ {
printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid); printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
} }
@ -201,7 +201,7 @@ static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other t
{ {
print_debug("started ap apicid: "); print_debug("started ap apicid: ");
for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0); for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
print_debug("\r\n"); print_debug("\n");
} }
static void allow_all_aps_stop(unsigned bsp_apicid) static void allow_all_aps_stop(unsigned bsp_apicid)
@ -286,8 +286,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
#endif #endif
if (cpu_init_detectedx) { if (cpu_init_detectedx) {
print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from "); print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from ");
print_debug("\r\nIssuing SOFT_RESET...\r\n"); print_debug("\nIssuing SOFT_RESET...\n");
soft_reset(); soft_reset();
} }
@ -351,7 +351,7 @@ static void wait_all_core0_started(void)
while(!is_core0_started(i)) {} while(!is_core0_started(i)) {}
print_initcpu8_nocr(" ", i); print_initcpu8_nocr(" ", i);
} }
print_debug("\r\n"); print_debug("\n");
} }

24
src/cpu/amd/model_lx/cpureginit.c
View File

@ -209,9 +209,9 @@ void SetDelayControl(void)
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug(" and lo "); print_debug(" and lo ");
print_debug_hex32(msr.lo); print_debug_hex32(msr.lo);
print_debug("\r\n"); print_debug("\n");
wrmsr(GLCP_DELAY_CONTROLS, msr); wrmsr(GLCP_DELAY_CONTROLS, msr);
print_debug("SetDelayControl done\r\n"); print_debug("SetDelayControl done\n");
return; return;
} }
@ -225,7 +225,7 @@ void cpuRegInit(void)
/* Castle 2.0 BTM periodic sync period. */ /* Castle 2.0 BTM periodic sync period. */
/* [40:37] 1 sync record per 256 bytes */ /* [40:37] 1 sync record per 256 bytes */
print_debug("Castle 2.0 BTM periodic sync period.\r\n"); print_debug("Castle 2.0 BTM periodic sync period.\n");
msrnum = CPU_PF_CONF; msrnum = CPU_PF_CONF;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.hi |= (0x8 << 5); msr.hi |= (0x8 << 5);
@ -235,7 +235,7 @@ void cpuRegInit(void)
* LX performance setting. * LX performance setting.
* Enable Quack for fewer re-RAS on the MC * Enable Quack for fewer re-RAS on the MC
*/ */
print_debug("Enable Quack for fewer re-RAS on the MC\r\n"); print_debug("Enable Quack for fewer re-RAS on the MC\n");
msrnum = GLIU0_ARB; msrnum = GLIU0_ARB;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.hi &= ~ARB_UPPER_DACK_EN_SET; msr.hi &= ~ARB_UPPER_DACK_EN_SET;
@ -251,25 +251,25 @@ void cpuRegInit(void)
/* GLIU port active enable, limit south pole masters /* GLIU port active enable, limit south pole masters
* (AES and PCI) to one outstanding transaction. * (AES and PCI) to one outstanding transaction.
*/ */
print_debug(" GLIU port active enable\r\n"); print_debug(" GLIU port active enable\n");
msrnum = GLIU1_PORT_ACTIVE; msrnum = GLIU1_PORT_ACTIVE;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo &= ~0x880; msr.lo &= ~0x880;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Set the Delay Control in GLCP */ /* Set the Delay Control in GLCP */
print_debug("Set the Delay Control in GLCP\r\n"); print_debug("Set the Delay Control in GLCP\n");
SetDelayControl(); SetDelayControl();
/* Enable RSDC */ /* Enable RSDC */
print_debug("Enable RSDC\r\n"); print_debug("Enable RSDC\n");
msrnum = CPU_AC_SMM_CTL; msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo |= SMM_INST_EN_SET; msr.lo |= SMM_INST_EN_SET;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* FPU imprecise exceptions bit */ /* FPU imprecise exceptions bit */
print_debug("FPU imprecise exceptions bit\r\n"); print_debug("FPU imprecise exceptions bit\n");
msrnum = CPU_FPU_MSR_MODE; msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET; msr.lo |= FPU_IE_SET;
@ -277,14 +277,14 @@ void cpuRegInit(void)
/* Power Savers (Do after BIST) */ /* Power Savers (Do after BIST) */
/* Enable Suspend on HLT & PAUSE instructions */ /* Enable Suspend on HLT & PAUSE instructions */
print_debug("Enable Suspend on HLT & PAUSE instructions\r\n"); print_debug("Enable Suspend on HLT & PAUSE instructions\n");
msrnum = CPU_XC_CONFIG; msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
print_debug("Enable SUSP and allow TSC to run in Suspend\r\n"); print_debug("Enable SUSP and allow TSC to run in Suspend\n");
msrnum = CPU_BC_CONF_0; msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
@ -302,10 +302,10 @@ void cpuRegInit(void)
#endif #endif
/* Setup throttling delays to proper mode if it is ever enabled. */ /* Setup throttling delays to proper mode if it is ever enabled. */
print_debug("Setup throttling delays to proper mode\r\n"); print_debug("Setup throttling delays to proper mode\n");
msrnum = GLCP_TH_OD; msrnum = GLCP_TH_OD;
msr.hi = 0; msr.hi = 0;
msr.lo = 0x00000603C; msr.lo = 0x00000603C;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
print_debug("Done cpuRegInit\r\n"); print_debug("Done cpuRegInit\n");
} }

2
src/cpu/amd/quadcore/amd_sibling.c
View File

@ -114,7 +114,7 @@ u32 get_apicid_base(u32 ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) { if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID // We need to enable APIC EXT ID
printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n"); printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n");
enable_apic_ext_id(sysconf.nodes); enable_apic_ext_id(sysconf.nodes);
} }

60
src/cpu/amd/sc520/raminit.c
View File

@ -248,14 +248,14 @@ udelay(int microseconds) {
static void dumpram(void){ static void dumpram(void){
print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n"); print_err("ctl "); print_err_hex8(*drcctl); print_err("\n");
print_err("mctl "); print_err_hex8(*drcmctl); print_err("\r\n"); print_err("mctl "); print_err_hex8(*drcmctl); print_err("\n");
print_err("cfg "); print_err_hex8(*drccfg); print_err("\r\n"); print_err("cfg "); print_err_hex8(*drccfg); print_err("\n");
print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\r\n"); print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\n");
print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\r\n"); print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\n");
print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\r\n"); print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\n");
print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\r\n"); print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n");
} }
/* there is a lot of silliness in the amd code, and it is /* there is a lot of silliness in the amd code, and it is
@ -311,11 +311,11 @@ int sizemem(void)
print_err("NOP\n"); print_err("NOP\n");
/* 100? 200? */ /* 100? 200? */
udelay(100); udelay(100);
print_err("after sc520_udelay\r\n"); print_err("after sc520_udelay\n");
/* issue all banks precharge */ /* issue all banks precharge */
*drcctl=0x02; *drcctl=0x02;
print_err("set *drcctl to 2 \r\n"); print_err("set *drcctl to 2 \n");
dummy_write(); dummy_write();
print_err("PRE\n"); print_err("PRE\n");
@ -334,7 +334,7 @@ int sizemem(void)
*drcctl=0x04; *drcctl=0x04;
for (i=0; i<8; i++) /* refresh 8 times */{ for (i=0; i<8; i++) /* refresh 8 times */{
dummy_write(); dummy_write();
print_err("dummy write\r\n"); print_err("dummy write\n");
} }
print_err("8 dummy writes\n"); print_err("8 dummy writes\n");
@ -342,18 +342,18 @@ int sizemem(void)
*drcctl=0x00; *drcctl=0x00;
print_err("normal\n"); print_err("normal\n");
print_err("HI done normal\r\n"); print_err("HI done normal\n");
print_err("sizemem\n"); print_err("sizemem\n");
for(bank = 3; bank >= 0; bank--) { for(bank = 3; bank >= 0; bank--) {
print_err("Try to assign to l\r\n"); print_err("Try to assign to l\n");
*lp = 0xdeadbeef; *lp = 0xdeadbeef;
print_err("assigned l ... \r\n"); print_err("assigned l ... \n");
if (*lp != 0xdeadbeef) { if (*lp != 0xdeadbeef) {
print_err(" no memory at bank "); print_err(" no memory at bank ");
// print_err_hex8(bank); // print_err_hex8(bank);
// print_err(" value "); print_err_hex32(*lp); // print_err(" value "); print_err_hex32(*lp);
print_err("\r\n"); print_err("\n");
// continue; // continue;
} }
*drcctl = 2; *drcctl = 2;
@ -362,7 +362,7 @@ int sizemem(void)
l = *drcbendadr; l = *drcbendadr;
l >>= 8; l >>= 8;
*drcbendadr = l; *drcbendadr = l;
print_err("loop around\r\n"); print_err("loop around\n");
*drcctl = 0; *drcctl = 0;
dummy_write(); dummy_write();
} }
@ -386,11 +386,11 @@ int sizemem(void)
print_err("NOP\n"); print_err("NOP\n");
/* 100? 200? */ /* 100? 200? */
//sc520_udelay(100); //sc520_udelay(100);
print_err("after sc520_udelay\r\n"); print_err("after sc520_udelay\n");
/* issue all banks precharge */ /* issue all banks precharge */
*drcctl=0x02; *drcctl=0x02;
print_err("set *drcctl to 2 \r\n"); print_err("set *drcctl to 2 \n");
dummy_write(); dummy_write();
print_err("PRE\n"); print_err("PRE\n");
@ -409,7 +409,7 @@ int sizemem(void)
*drcctl=0x04; *drcctl=0x04;
for (i=0; i<8; i++) /* refresh 8 times */{ for (i=0; i<8; i++) /* refresh 8 times */{
dummy_write(); dummy_write();
print_err("dummy write\r\n"); print_err("dummy write\n");
} }
print_err("8 dummy writes\n"); print_err("8 dummy writes\n");
@ -417,7 +417,7 @@ int sizemem(void)
*drcctl=0x00; *drcctl=0x00;
print_err("normal\n"); print_err("normal\n");
print_err("HI done normal\r\n"); print_err("HI done normal\n");
bank = 3; bank = 3;
@ -558,7 +558,7 @@ print_err("4b\n");
al -= i&3; al -= i&3;
*drcbendaddr = rows >> al; *drcbendaddr = rows >> al;
print_err("computed ending_adr = "); print_err_hex8(ending_adr); print_err("computed ending_adr = "); print_err_hex8(ending_adr);
print_err("\r\n"); print_err("\n");
*/ */
bad_reinit: bad_reinit:
@ -592,7 +592,7 @@ bad_reinit:
return bank; return bank;
bad_ram: bad_ram:
print_info("bad ram!\r\n"); print_info("bad ram!\n");
/* you are here because the read-after-write failed, /* you are here because the read-after-write failed,
* in most cases because: no ram in that bank! * in most cases because: no ram in that bank!
* set badbank to 1 and go to reinit * set badbank to 1 and go to reinit
@ -600,7 +600,7 @@ bad_ram:
ending_adr = 0; ending_adr = 0;
goto bad_reinit; goto bad_reinit;
while(1) while(1)
print_err("DONE NEXTBANK\r\n"); print_err("DONE NEXTBANK\n");
#endif #endif
} }
@ -628,27 +628,27 @@ int staticmem(void)
/* two autorefreshes */ /* two autorefreshes */
*drcctl = 4; *drcctl = 4;
*zero = 0; *zero = 0;
print_debug("one zero out on refresh\r\n"); print_debug("one zero out on refresh\n");
*zero = 0; *zero = 0;
print_debug("two zero out on refresh\r\n"); print_debug("two zero out on refresh\n");
/* load mode register */ /* load mode register */
*drcctl = 3; *drcctl = 3;
*zero = 0; *zero = 0;
print_debug("DONE the load mode reg\r\n"); print_debug("DONE the load mode reg\n");
/* normal mode */ /* normal mode */
*drcctl = 0x0; *drcctl = 0x0;
*zero = 0; *zero = 0;
print_debug("DONE one last write and then turn on refresh etc\r\n"); print_debug("DONE one last write and then turn on refresh etc\n");
*drcctl = 0x18; *drcctl = 0x18;
*zero = 0; *zero = 0;
print_debug("DONE the normal\r\n"); print_debug("DONE the normal\n");
*zero = 0xdeadbeef; *zero = 0xdeadbeef;
if (*zero != 0xdeadbeef) if (*zero != 0xdeadbeef)
print_debug("NO LUCK\r\n"); print_debug("NO LUCK\n");
else else
print_debug("did a store and load ...\r\n"); print_debug("did a store and load ...\n");
//print_err_hex32(*zero); //print_err_hex32(*zero);
// print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n"); // print_err(" zero is now "); print_err_hex32(*zero); print_err("\n");
} }

4
src/cpu/intel/microcode/microcode.c
View File

@ -82,7 +82,7 @@ void intel_update_microcode(const void *microcode_updates)
print_debug_hex32(pf); print_debug_hex32(pf);
print_debug(" rev = 0x"); print_debug(" rev = 0x");
print_debug_hex32(rev); print_debug_hex32(rev);
print_debug("\r\n"); print_debug("\n");
m = microcode_updates; m = microcode_updates;
for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {
@ -99,7 +99,7 @@ void intel_update_microcode(const void *microcode_updates)
print_debug_hex32(new_rev); print_debug_hex32(new_rev);
print_debug(" from revision "); print_debug(" from revision ");
print_debug_hex32(rev); print_debug_hex32(rev);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
if (m->total_size) { if (m->total_size) {

8
src/cpu/intel/model_106cx/cache_as_ram_disable.c
View File

@ -40,10 +40,10 @@ void stage1_main(unsigned long bist)
"movl %%esp, %0\n\t" "movl %%esp, %0\n\t"
: "=a" (v_esp) : "=a" (v_esp)
); );
printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp); printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
} }
printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset); printk(BIOS_SPEW, "cpu_reset = %08x\n",cpu_reset);
if(cpu_reset == 0) { if(cpu_reset == 0) {
print_spew("Clearing initial memory region: "); print_spew("Clearing initial memory region: ");
@ -83,12 +83,12 @@ void stage1_main(unsigned long bist)
#ifdef CONFIG_DEACTIVATE_CAR #ifdef CONFIG_DEACTIVATE_CAR
print_debug("Deactivating CAR"); print_debug("Deactivating CAR");
#include CONFIG_DEACTIVATE_CAR_FILE #include CONFIG_DEACTIVATE_CAR_FILE
print_debug(" - Done.\r\n"); print_debug(" - Done.\n");
#endif #endif
/* Copy and execute coreboot_ram */ /* Copy and execute coreboot_ram */
copy_and_run(new_cpu_reset); copy_and_run(new_cpu_reset);
/* We will not return */ /* We will not return */
} }
print_debug("sorry. parachute did not open.\r\n"); print_debug("sorry. parachute did not open.\n");
} }

4
src/drivers/ati/ragexl/xlinit.c
View File

@ -541,7 +541,7 @@ static void ati_ragexl_init(device_t dev)
#endif #endif
#if 0 #if 0
printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer); printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
#endif #endif
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info); chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
@ -561,7 +561,7 @@ static void ati_ragexl_init(device_t dev)
return ; return ;
found: found:
printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev); printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);
#if 0 #if 0
if (M64_HAS(INTEGRATED)) { if (M64_HAS(INTEGRATED)) {
/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */

6
src/drivers/generic/debug/debug_dev.c
View File

@ -92,16 +92,16 @@ static void print_smbus_regs(struct device *dev)
unsigned char byte; unsigned char byte;
status = smbus_read_byte(dev, j); status = smbus_read_byte(dev, j);
if (status < 0) { if (status < 0) {
// printk(BIOS_DEBUG, "bad device status= %08x\r\n", status); // printk(BIOS_DEBUG, "bad device status= %08x\n", status);
break; break;
} }
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
printk(BIOS_DEBUG, "\r\n%02x: ", j); printk(BIOS_DEBUG, "\n%02x: ", j);
} }
byte = status & 0xff; byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte); printk(BIOS_DEBUG, "%02x ", byte);
} }
printk(BIOS_DEBUG, "\r\n"); printk(BIOS_DEBUG, "\n");
} }
static void print_smbus_regs_all(struct device *dev) static void print_smbus_regs_all(struct device *dev)

6
src/drivers/i2c/adm1027/adm1027.c
View File

@ -26,7 +26,7 @@ static void adm1027_enable_monitoring(device_t dev)
result = smbus_read_byte(dev, ADM1027_REG_CONFIG1); result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
if (!(result & CFG1_RDY)) { if (!(result & CFG1_RDY)) {
printk(BIOS_DEBUG, "ADM1027: monitoring not ready\r\n"); printk(BIOS_DEBUG, "ADM1027: monitoring not ready\n");
return; return;
} }
result = (result | CFG1_STRT); result = (result | CFG1_STRT);
@ -34,9 +34,9 @@ static void adm1027_enable_monitoring(device_t dev)
result = smbus_read_byte(dev, ADM1027_REG_CONFIG1); result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
if (!(result & CFG1_STRT)) { if (!(result & CFG1_STRT)) {
printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\r\n"); printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\n");
} }
printk(BIOS_DEBUG, "ADM1027: monitoring enabled\r\n"); printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n");
} }
static void adm1027_init(device_t dev) static void adm1027_init(device_t dev)

4
src/include/assert.h
View File

@ -29,7 +29,7 @@
print_emerg(__FILE__); \ print_emerg(__FILE__); \
print_emerg("', line 0x"); \ print_emerg("', line 0x"); \
print_debug_hex32(__LINE__); \ print_debug_hex32(__LINE__); \
print_emerg("\r\n"); \ print_emerg("\n"); \
/* die(""); */ \ /* die(""); */ \
} \ } \
} }
@ -39,7 +39,7 @@
print_emerg(__FILE__); \ print_emerg(__FILE__); \
print_emerg("', line 0x"); \ print_emerg("', line 0x"); \
print_debug_hex32(__LINE__); \ print_debug_hex32(__LINE__); \
print_emerg("\r\n"); \ print_emerg("\n"); \
/* die(""); */ \ /* die(""); */ \
} }

2
src/include/cpu/x86/bist.h
View File

@ -10,7 +10,7 @@ static void report_bist_failure(u32 bist)
print_emerg("BIST failed: "); print_emerg("BIST failed: ");
print_emerg_hex32(bist); print_emerg_hex32(bist);
#endif #endif
die("\r\n"); die("\n");
} }
} }

6
src/lib/debug.c
View File

@ -23,7 +23,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -31,7 +31,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -43,7 +43,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }

14
src/lib/generic_dump_spd.c
View File

@ -6,7 +6,7 @@
static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\r\n"); print_debug("\n");
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
device = ctrl->channel0[i]; device = ctrl->channel0[i];
@ -20,20 +20,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = spd_read_byte(device, j); status = spd_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
@ -46,20 +46,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = spd_read_byte(device, j); status = spd_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }

6
src/lib/generic_sdram.c
View File

@ -9,7 +9,7 @@ static inline void print_debug_sdram_8(const char *strval, uint32_t val)
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "%s%02x\n", strval, val); printk(BIOS_DEBUG, "%s%02x\n", strval, val);
#else #else
print_debug(strval); print_debug_hex8(val); print_debug("\r\n"); print_debug(strval); print_debug_hex8(val); print_debug("\n");
#endif #endif
} }
@ -48,7 +48,7 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl)
* Some chipsets do the work for us while on others * Some chipsets do the work for us while on others
* we need to it by hand. * we need to it by hand.
*/ */
print_debug("Ram3\r\n"); print_debug("Ram3\n");
#if RAMINIT_SYSINFO == 1 #if RAMINIT_SYSINFO == 1
sdram_enable(controllers, ctrl, sysinfo); sdram_enable(controllers, ctrl, sysinfo);
@ -56,5 +56,5 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl)
sdram_enable(controllers, ctrl); sdram_enable(controllers, ctrl);
#endif #endif
print_debug("Ram4\r\n"); print_debug("Ram4\n");
} }

36
src/lib/ramtest.c
View File

@ -52,13 +52,13 @@ static void ram_fill(unsigned long start, unsigned long stop)
* Fill. * Fill.
*/ */
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop); printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop);
#else #else
print_debug("DRAM fill: "); print_debug("DRAM fill: ");
print_debug_hex32(start); print_debug_hex32(start);
print_debug("-"); print_debug("-");
print_debug_hex32(stop); print_debug_hex32(stop);
print_debug("\r\n"); print_debug("\n");
#endif #endif
for(addr = start; addr < stop ; addr += 4) { for(addr = start; addr < stop ; addr += 4) {
/* Display address being filled */ /* Display address being filled */
@ -74,10 +74,10 @@ static void ram_fill(unsigned long start, unsigned long stop)
}; };
/* Display final address */ /* Display final address */
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "%08lx\r\nDRAM filled\r\n", addr); printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr);
#else #else
print_debug_hex32(addr); print_debug_hex32(addr);
print_debug("\r\nDRAM filled\r\n"); print_debug("\nDRAM filled\n");
#endif #endif
} }
@ -89,13 +89,13 @@ static void ram_verify(unsigned long start, unsigned long stop)
* Verify. * Verify.
*/ */
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop); printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop);
#else #else
print_debug("DRAM verify: "); print_debug("DRAM verify: ");
print_debug_hex32(start); print_debug_hex32(start);
print_debug_char('-'); print_debug_char('-');
print_debug_hex32(stop); print_debug_hex32(stop);
print_debug("\r\n"); print_debug("\n");
#endif #endif
for(addr = start; addr < stop ; addr += 4) { for(addr = start; addr < stop ; addr += 4) {
unsigned long value; unsigned long value;
@ -112,20 +112,20 @@ static void ram_verify(unsigned long start, unsigned long stop)
if (value != addr) { if (value != addr) {
/* Display address with error */ /* Display address with error */
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value); printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value);
#else #else
print_err("Fail: @0x"); print_err("Fail: @0x");
print_err_hex32(addr); print_err_hex32(addr);
print_err(" Read value=0x"); print_err(" Read value=0x");
print_err_hex32(value); print_err_hex32(value);
print_err("\r\n"); print_err("\n");
#endif #endif
i++; i++;
if(i>256) { if(i>256) {
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "Aborting.\n\r"); printk(BIOS_DEBUG, "Aborting.\n");
#else #else
print_debug("Aborting.\n\r"); print_debug("Aborting.\n");
#endif #endif
break; break;
} }
@ -140,17 +140,17 @@ static void ram_verify(unsigned long start, unsigned long stop)
if (i) { if (i) {
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "\r\nDRAM did _NOT_ verify!\r\n"); printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
#else #else
print_debug("\r\nDRAM did _NOT_ verify!\r\n"); print_debug("\nDRAM did _NOT_ verify!\n");
#endif #endif
die("DRAM ERROR"); die("DRAM ERROR");
} }
else { else {
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "\r\nDRAM range verified.\r\n"); printk(BIOS_DEBUG, "\nDRAM range verified.\n");
#else #else
print_debug("\r\nDRAM range verified.\r\n"); print_debug("\nDRAM range verified.\n");
#endif #endif
} }
} }
@ -164,22 +164,22 @@ void ram_check(unsigned long start, unsigned long stop)
* are tested. -Tyson * are tested. -Tyson
*/ */
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\r\n", start, stop); printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop);
#else #else
print_debug("Testing DRAM : "); print_debug("Testing DRAM : ");
print_debug_hex32(start); print_debug_hex32(start);
print_debug("-"); print_debug("-");
print_debug_hex32(stop); print_debug_hex32(stop);
print_debug("\r\n"); print_debug("\n");
#endif #endif
ram_fill(start, stop); ram_fill(start, stop);
/* Make sure we don't read before we wrote */ /* Make sure we don't read before we wrote */
phys_memory_barrier(); phys_memory_barrier();
ram_verify(start, stop); ram_verify(start, stop);
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "Done.\r\n"); printk(BIOS_DEBUG, "Done.\n");
#else #else
print_debug("Done.\r\n"); print_debug("Done.\n");
#endif #endif
} }

2
src/mainboard/amd/dbm690t/romstage.c
View File

@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/amd/mahogany/romstage.c
View File

@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/amd/pistachio/romstage.c
View File

@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x06); post_code(0x06);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

6
src/mainboard/amd/rumba/romstage.c
View File

@ -50,7 +50,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* get module banks (sides) per dimm, SPD byte 5 */ /* get module banks (sides) per dimm, SPD byte 5 */
module_banks = spd_read_byte(0xA0, 5); module_banks = spd_read_byte(0xA0, 5);
if (module_banks < 1 || module_banks > 2) if (module_banks < 1 || module_banks > 2)
print_err("Module banks per dimm\r\n"); print_err("Module banks per dimm\n");
module_banks >>= 1; module_banks >>= 1;
msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
@ -58,7 +58,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* get component banks per module bank, SPD byte 17 */ /* get component banks per module bank, SPD byte 17 */
val = spd_read_byte(0xA0, 17); val = spd_read_byte(0xA0, 17);
if (val < 2 || val > 4) if (val < 2 || val > 4)
print_err("Component banks per module bank\r\n"); print_err("Component banks per module bank\n");
val >>= 2; val >>= 2;
msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
@ -78,7 +78,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
print_debug("computed msr.hi "); print_debug("computed msr.hi ");
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug("\r\n"); print_debug("\n");
msr.lo = 0x00003000; msr.lo = 0x00003000;
wrmsr(MC_CF07_DATA, msr); wrmsr(MC_CF07_DATA, msr);

2
src/mainboard/amd/serengeti_cheetah/ap_romstage.c
View File

@ -69,7 +69,7 @@ void hardwaremain(int ret_addr)
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n"); printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
#else #else
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
#endif #endif
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);

14
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -92,14 +92,14 @@ static inline void change_i2c_mux(unsigned device)
{ {
#define SMBUS_HUB 0x18 #define SMBUS_HUB 0x18
int ret, i; int ret, i;
print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
i=2; i=2;
do { do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device); ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
} while ((ret!=0) && (i-->0)); } while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
} }
#endif #endif
@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device(PCI_DEV(0, 0x19, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif #endif
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -246,7 +246,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Read FIDVID_STATUS */ /* Read FIDVID_STATUS */
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -276,7 +276,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
} }
#endif #endif

20
src/mainboard/arima/hdama/debug.c
View File

@ -23,7 +23,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -31,7 +31,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -43,7 +43,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -70,7 +70,7 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr
int n; int n;
for(n = 0; n < controllers; n++) { for(n = 0; n < controllers; n++) {
int i; int i;
print_debug("\r\n"); print_debug("\n");
activate_spd_rom(&ctrl[n]); activate_spd_rom(&ctrl[n]);
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
@ -87,13 +87,13 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = spd_read_byte(device, j); status = spd_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
#if 0 #if 0
@ -104,7 +104,7 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr
#endif #endif
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl[n].channel1[i]; device = ctrl[n].channel1[i];
if (device) { if (device) {
@ -119,13 +119,13 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = spd_read_byte(device, j); status = spd_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
#if 0 #if 0
@ -136,7 +136,7 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr
#endif #endif
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }

2
src/mainboard/arima/hdama/romstage.c
View File

@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/asus/a8n_e/romstage.c
View File

@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

10
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -89,7 +89,7 @@ void soft_reset(void)
uint8_t tmp; uint8_t tmp;
set_bios_reset(); set_bios_reset();
print_debug("soft reset \r\n"); print_debug("soft reset \n");
/* PCI reset */ /* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init(); console_init();
enable_rom_decode(); enable_rom_decode();
print_info("now booting... fallback\r\n"); print_info("now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */ /* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
@ -210,7 +210,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init(); console_init();
enable_rom_decode(); enable_rom_decode();
print_info("now booting... real_main\r\n"); print_info("now booting... real_main\n");
if (bist == 0) if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@ -222,7 +222,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); setup_coherent_ht_domain();
wait_all_core0_started(); wait_all_core0_started();
print_info("now booting... Core0 started\r\n"); print_info("now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
/* It is said that we should start core1 after all core0 launched. */ /* It is said that we should start core1 after all core0 launched. */
@ -237,7 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= k8t890_early_setup_ht(); needs_reset |= k8t890_early_setup_ht();
if (needs_reset) { if (needs_reset) {
print_debug("ht reset -\r\n"); print_debug("ht reset -\n");
soft_reset(); soft_reset();
} }

16
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -105,12 +105,12 @@ void activate_spd_rom(const struct mem_controller *ctrl)
/* this function might fail on some K8 CPUs with errata #181 */ /* this function might fail on some K8 CPUs with errata #181 */
static void ldtstop_sb(void) static void ldtstop_sb(void)
{ {
print_debug("toggle LDTSTP#\r\n"); print_debug("toggle LDTSTP#\n");
u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
reg = reg ^ (1 << 0); reg = reg ^ (1 << 0);
outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
reg = inb(VT8237R_ACPI_IO_BASE + 0x15); reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
print_debug("done\r\n"); print_debug("done\n");
} }
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
@ -127,7 +127,7 @@ void soft_reset(void)
uint8_t tmp; uint8_t tmp;
set_bios_reset(); set_bios_reset();
print_debug("soft reset \r\n"); print_debug("soft reset \n");
/* PCI reset */ /* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@ -188,7 +188,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init(); console_init();
enable_rom_decode(); enable_rom_decode();
print_info("now booting... real_main\r\n"); print_info("now booting... real_main\n");
if (bist == 0) if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@ -199,7 +199,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); setup_coherent_ht_domain();
wait_all_core0_started(); wait_all_core0_started();
print_info("now booting... Core0 started\r\n"); print_info("now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
/* It is said that we should start core1 after all core0 launched. */ /* It is said that we should start core1 after all core0 launched. */
@ -222,9 +222,9 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (needs_reset) { if (needs_reset) {
print_debug_hex8(needs_reset); print_debug_hex8(needs_reset);
print_debug("Xht reset -\r\n"); print_debug("Xht reset -\n");
soft_reset(); soft_reset();
print_debug("NO reset\r\n"); print_debug("NO reset\n");
} }
@ -233,7 +233,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
vt8237_sb_enable_fid_vid(); vt8237_sb_enable_fid_vid();
enable_fid_change(); enable_fid_change();
print_debug("after enable_fid_change\r\n"); print_debug("after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);

8
src/mainboard/bcom/winnetp680/romstage.c
View File

@ -101,26 +101,26 @@ static void main(unsigned long bist)
uart_init(); uart_init();
console_init(); console_init();
print_spew("In romstage.c:main()\r\n"); print_spew("In romstage.c:main()\n");
enable_smbus(); enable_smbus();
smbus_fixup(&ctrl); smbus_fixup(&ctrl);
if (bist == 0) { if (bist == 0) {
print_debug("doing early_mtrr\r\n"); print_debug("doing early_mtrr\n");
early_mtrr_init(); early_mtrr_init();
} }
/* Halt if there was a built-in self test failure. */ /* Halt if there was a built-in self test failure. */
report_bist_failure(bist); report_bist_failure(bist);
print_debug("Enabling mainboard devices\r\n"); print_debug("Enabling mainboard devices\n");
enable_mainboard_devices(); enable_mainboard_devices();
ddr_ram_setup(&ctrl); ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */ /* ram_check(0, 640 * 1024); */
print_spew("Leaving romstage.c:main()\r\n"); print_spew("Leaving romstage.c:main()\n");
} }

8
src/mainboard/broadcom/blast/romstage.c
View File

@ -70,9 +70,9 @@ static inline void change_i2c_mux(unsigned device)
{ {
#define SMBUS_HUB 0x71 #define SMBUS_HUB 0x71
int ret; int ret;
print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
ret = smbus_send_byte(SMBUS_HUB, device); ret = smbus_send_byte(SMBUS_HUB, device);
print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
} }
#endif #endif
@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
setup_blast_resource_map(); setup_blast_resource_map();
@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bcm5785_early_setup(); bcm5785_early_setup();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

54
src/mainboard/dell/s1850/debug.c
View File

@ -12,7 +12,7 @@ static void print_reg(unsigned char index)
print_debug_hex8(index); print_debug_hex8(index);
print_debug(": 0x"); print_debug(": 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
return; return;
} }
@ -49,52 +49,52 @@ static void siodump(void)
int i; int i;
unsigned char data; unsigned char data;
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
print_debug("\r\n*** XBUS REGISTERS ***\r\n"); print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03); setup_func(0x03);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02); setup_func(0x02);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
print_debug("\r\n*** GPIO REGISTERS ***\r\n"); print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** GPIO VALUES ***\r\n"); print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a); data = inb(0x68a);
print_debug("\r\nGPDO 4: 0x"); print_debug("\nGPDO 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
data = inb(0x68b); data = inb(0x68b);
print_debug("\r\nGPDI 4: 0x"); print_debug("\nGPDI 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
#if 0 #if 0
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a); setup_func(0x0a);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09); setup_func(0x09);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
print_debug("\r\n*** RTC REGISTERS ***\r\n"); print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10); setup_func(0x10);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
@ -104,7 +104,7 @@ static void siodump(void)
print_reg(0xfe); print_reg(0xfe);
print_reg(0xff); print_reg(0xff);
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14); setup_func(0x14);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
@ -135,7 +135,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev)
int i; int i;
unsigned long bar; unsigned long bar;
print_debug("BAR 14 Dump\r\n"); print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14); bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) { for(i = 0; i <= 0x300; i+=4) {
@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#endif #endif
if((i%4)==0) { if((i%4)==0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex16(i); print_debug_hex16(i);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug_hex32(read32(bar + i)); print_debug_hex32(read32(bar + i));
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
static void dump_pci_devices(void) static void dump_pci_devices(void)
@ -212,14 +212,14 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
unsigned char byte; unsigned char byte;
if ((i % 16) == 0) { if ((i % 16) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(i); print_debug_hex8(i);
print_debug(": "); print_debug(": ");
} }
@ -227,7 +227,7 @@ void dump_spd_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);
@ -245,7 +245,7 @@ void show_dram_slots(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
@ -256,7 +256,7 @@ void show_dram_slots(void)
print_debug("present: "); print_debug("present: ");
} }
print_debug_hex8(status); print_debug_hex8(status);
print_debug("\r\n"); print_debug("\n");
device += SMBUS_MEM_DEVICE_INC; device += SMBUS_MEM_DEVICE_INC;
print_debug("\n"); print_debug("\n");
} }
@ -269,7 +269,7 @@ void dump_ipmi_registers(void)
while(device <= 0x42) { while(device <= 0x42) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("ipmi "); print_debug("ipmi ");
print_debug_hex8(device); print_debug_hex8(device);
@ -279,7 +279,7 @@ void dump_ipmi_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);

2
src/mainboard/dell/s1850/watchdog.c
View File

@ -52,6 +52,6 @@ static void disable_watchdogs(void)
{ {
// disable_sio_watchdog(NSC_WD_DEV); // disable_sio_watchdog(NSC_WD_DEV);
disable_ich5_watchdog(); disable_ich5_watchdog();
print_debug("Watchdogs disabled\r\n"); print_debug("Watchdogs disabled\n");
} }

20
src/mainboard/digitallogic/msm586seg/romstage.c
View File

@ -80,7 +80,7 @@ static inline void dumpmem(void){
print_err_hex8(c); print_err_hex8(c);
print_err(" "); print_err(" ");
} }
print_err("\r\n"); print_err("\n");
} }
} }
@ -190,16 +190,16 @@ static void main(unsigned long bist)
uart_init(); uart_init();
console_init(); console_init();
for(i = 0; i < 100; i++) for(i = 0; i < 100; i++)
print_err("fill usart\r\n"); print_err("fill usart\n");
// while(1) // while(1)
print_err("HI THERE!\r\n"); print_err("HI THERE!\n");
// sizemem(); // sizemem();
staticmem(); staticmem();
print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60);
print_err("\n"); print_err("\n");
// while(1) // while(1)
print_err("STATIC MEM DONE\r\n"); print_err("STATIC MEM DONE\n");
outb(0xee, 0x80); outb(0xee, 0x80);
print_err("loop forever ...\n"); print_err("loop forever ...\n");
@ -227,12 +227,12 @@ static void main(unsigned long bist)
#endif #endif
#if 0 #if 0
print_err("RAM CHECK!\r\n"); print_err("RAM CHECK!\n");
// Check 16MB of memory @ 0 // Check 16MB of memory @ 0
ram_check(0x00000000, 0x01000000); ram_check(0x00000000, 0x01000000);
#endif #endif
#if 0 #if 0
print_err("RAM CHECK for 32 MB!\r\n"); print_err("RAM CHECK for 32 MB!\n");
// Check 32MB of memory @ 0 // Check 32MB of memory @ 0
ram_check(0x00000000, 0x02000000); ram_check(0x00000000, 0x02000000);
#endif #endif
@ -243,17 +243,17 @@ static void main(unsigned long bist)
for(i = 0; i < 0x20000; i++) { for(i = 0; i < 0x20000; i++) {
/* /*
print_err("Set dst "); print_err_hex32((unsigned long) dst); print_err("Set dst "); print_err_hex32((unsigned long) dst);
print_err(" to "); print_err_hex32(*src); print_err("\r\n"); print_err(" to "); print_err_hex32(*src); print_err("\n");
*/ */
*dst = *src; *dst = *src;
//print_err(" dst is now "); print_err_hex32(*dst); print_err("\r\n"); //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n");
dst++, src++; dst++, src++;
outb((unsigned char)i, 0x80); outb((unsigned char)i, 0x80);
} }
} }
dumpmem(); dumpmem();
outb(0, 0x80); outb(0, 0x80);
print_err("loop forever\r\n"); print_err("loop forever\n");
outb(0xdd, 0x80); outb(0xdd, 0x80);
__asm__ volatile( __asm__ volatile(
"movl %0, %%edi\n\t" "movl %0, %%edi\n\t"
@ -262,7 +262,7 @@ static void main(unsigned long bist)
: "a" (0x4000) : "a" (0x4000)
); );
print_err("Oh dear, I'm afraid it didn't work...\r\n"); print_err("Oh dear, I'm afraid it didn't work...\n");
while(1); while(1);
#endif #endif

2
src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
View File

@ -84,7 +84,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x(); id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);

8
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -215,7 +215,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init(); console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -241,7 +241,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -265,7 +265,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);

2
src/mainboard/gigabyte/m57sli/ap_romstage.c
View File

@ -82,7 +82,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x(); id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);

8
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init(); console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -254,7 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -268,7 +268,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -279,7 +279,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);

8
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -230,7 +230,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -256,7 +256,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
enable_fid_change(); enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@ -265,7 +265,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -274,7 +274,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/ibm/e325/romstage.c
View File

@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/ibm/e326/romstage.c
View File

@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

64
src/mainboard/intel/eagleheights/debug.c
View File

@ -34,7 +34,7 @@ static void print_reg(unsigned char index)
print_debug_hex8(index); print_debug_hex8(index);
print_debug(": 0x"); print_debug(": 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
return; return;
} }
@ -71,52 +71,52 @@ static void siodump(void)
int i; int i;
unsigned char data; unsigned char data;
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
print_debug("\r\n*** XBUS REGISTERS ***\r\n"); print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03); setup_func(0x03);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02); setup_func(0x02);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
print_debug("\r\n*** GPIO REGISTERS ***\r\n"); print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** GPIO VALUES ***\r\n"); print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a); data = inb(0x68a);
print_debug("\r\nGPDO 4: 0x"); print_debug("\nGPDO 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
data = inb(0x68b); data = inb(0x68b);
print_debug("\r\nGPDI 4: 0x"); print_debug("\nGPDI 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
#if 0 #if 0
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a); setup_func(0x0a);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09); setup_func(0x09);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
print_debug("\r\n*** RTC REGISTERS ***\r\n"); print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10); setup_func(0x10);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
@ -126,7 +126,7 @@ static void siodump(void)
print_reg(0xfe); print_reg(0xfe);
print_reg(0xff); print_reg(0xff);
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14); setup_func(0x14);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
@ -157,7 +157,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -165,7 +165,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -177,7 +177,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -187,7 +187,7 @@ static void dump_bar14(unsigned dev)
int i; int i;
unsigned long bar; unsigned long bar;
print_debug("BAR 14 Dump\r\n"); print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14); bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) { for(i = 0; i <= 0x300; i+=4) {
@ -200,14 +200,14 @@ static void dump_bar14(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#endif #endif
if((i%4)==0) { if((i%4)==0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex16(i); print_debug_hex16(i);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug_hex32(read32(bar + i)); print_debug_hex32(read32(bar + i));
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
static void dump_pci_devices(void) static void dump_pci_devices(void)
@ -231,7 +231,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\r\n"); print_debug("\n");
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
device = ctrl->channel0[i]; device = ctrl->channel0[i];
@ -245,20 +245,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
@ -271,20 +271,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -297,13 +297,13 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
if ((i % 16) == 0) { if ((i % 16) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(i); print_debug_hex8(i);
print_debug(": "); print_debug(": ");
} }
@ -311,7 +311,7 @@ void dump_spd_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);
@ -329,7 +329,7 @@ void dump_ipmi_registers(void)
while(device <= 0x42) { while(device <= 0x42) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("ipmi "); print_debug("ipmi ");
print_debug_hex8(device); print_debug_hex8(device);
@ -338,7 +338,7 @@ void dump_ipmi_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);

64
src/mainboard/intel/jarrell/debug.c
View File

@ -12,7 +12,7 @@ static void print_reg(unsigned char index)
print_debug_hex8(index); print_debug_hex8(index);
print_debug(": 0x"); print_debug(": 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
return; return;
} }
@ -49,52 +49,52 @@ static void siodump(void)
int i; int i;
unsigned char data; unsigned char data;
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
print_debug("\r\n*** XBUS REGISTERS ***\r\n"); print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03); setup_func(0x03);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02); setup_func(0x02);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
print_debug("\r\n*** GPIO REGISTERS ***\r\n"); print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** GPIO VALUES ***\r\n"); print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a); data = inb(0x68a);
print_debug("\r\nGPDO 4: 0x"); print_debug("\nGPDO 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
data = inb(0x68b); data = inb(0x68b);
print_debug("\r\nGPDI 4: 0x"); print_debug("\nGPDI 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
#if 0 #if 0
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a); setup_func(0x0a);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09); setup_func(0x09);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
print_debug("\r\n*** RTC REGISTERS ***\r\n"); print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10); setup_func(0x10);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
@ -104,7 +104,7 @@ static void siodump(void)
print_reg(0xfe); print_reg(0xfe);
print_reg(0xff); print_reg(0xff);
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14); setup_func(0x14);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
@ -135,7 +135,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev)
int i; int i;
unsigned long bar; unsigned long bar;
print_debug("BAR 14 Dump\r\n"); print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14); bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) { for(i = 0; i <= 0x300; i+=4) {
@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#endif #endif
if((i%4)==0) { if((i%4)==0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex16(i); print_debug_hex16(i);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug_hex32(read32(bar + i)); print_debug_hex32(read32(bar + i));
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
static void dump_pci_devices(void) static void dump_pci_devices(void)
@ -209,7 +209,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\r\n"); print_debug("\n");
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
device = ctrl->channel0[i]; device = ctrl->channel0[i];
@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -275,14 +275,14 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
unsigned char byte; unsigned char byte;
if ((i % 16) == 0) { if ((i % 16) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(i); print_debug_hex8(i);
print_debug(": "); print_debug(": ");
} }
@ -290,7 +290,7 @@ void dump_spd_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);
@ -308,7 +308,7 @@ void dump_ipmi_registers(void)
while(device <= 0x42) { while(device <= 0x42) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("ipmi "); print_debug("ipmi ");
print_debug_hex8(device); print_debug_hex8(device);
@ -318,7 +318,7 @@ void dump_ipmi_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);

4
src/mainboard/intel/jarrell/jarrell_fixups.c
View File

@ -58,12 +58,12 @@ static void mainboard_set_e7520_pll(unsigned bits)
/* set gpio 42,44 signal levels */ /* set gpio 42,44 signal levels */
data = inb(gpio_index + PC87427_GPDO_4); data = inb(gpio_index + PC87427_GPDO_4);
if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) { if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
print_debug("set_pllsel: correct settings detected!\r\n"); print_debug("set_pllsel: correct settings detected!\n");
return; /* settings already configured */ return; /* settings already configured */
} else { } else {
outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4); outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
/* reset */ /* reset */
print_debug("set_pllsel: settings adjusted, now resetting...\r\n"); print_debug("set_pllsel: settings adjusted, now resetting...\n");
// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */ // hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
// mch_reset(); // mch_reset();
full_reset(); full_reset();

2
src/mainboard/intel/jarrell/power_reset_check.c
View File

@ -6,7 +6,7 @@ static void power_down_reset_check(void)
cmos=cmos_read(RTC_BOOT_BYTE)>>4 ; cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
print_debug("Boot byte = "); print_debug("Boot byte = ");
print_debug_hex8(cmos); print_debug_hex8(cmos);
print_debug("\r\n"); print_debug("\n");
if((cmos>2)&&(cmos&1)) full_reset(); if((cmos>2)&&(cmos&1)) full_reset();
} }

4
src/mainboard/intel/jarrell/watchdog.c
View File

@ -91,7 +91,7 @@ static void disable_watchdogs(void)
disable_sio_watchdog(NSC_WD_DEV); disable_sio_watchdog(NSC_WD_DEV);
disable_ich5_watchdog(); disable_ich5_watchdog();
disable_jarell_frb3(); disable_jarell_frb3();
print_debug("Watchdogs disabled\r\n"); print_debug("Watchdogs disabled\n");
} }
static void ich5_watchdog_on(void) static void ich5_watchdog_on(void)
@ -134,5 +134,5 @@ static void ich5_watchdog_on(void)
value &= ~(1 << 11); value &= ~(1 << 11);
outw(value, base + 0x08); outw(value, base + 0x08);
print_debug("Watchdog ICH5 enabled\r\n"); print_debug("Watchdog ICH5 enabled\n");
} }

2
src/mainboard/intel/xe7501devkit/romstage.c
View File

@ -86,6 +86,6 @@ static void main(unsigned long bist)
// NOTE: ROMCC dies with an internal compiler error // NOTE: ROMCC dies with an internal compiler error
// if the following line is removed. // if the following line is removed.
print_debug("SDRAM is up.\r\n"); print_debug("SDRAM is up.\n");
} }

8
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_mb_resource_map(); setup_mb_resource_map();
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -207,7 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -217,7 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
} }

8
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_default_resource_map(); setup_default_resource_map();
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -207,7 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -217,7 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
} }

8
src/mainboard/iwill/dk8x/romstage.c
View File

@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_default_resource_map(); setup_default_resource_map();
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -207,7 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -217,7 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
} }

8
src/mainboard/jetway/j7f24/romstage.c
View File

@ -103,26 +103,26 @@ static void main(unsigned long bist)
uart_init(); uart_init();
console_init(); console_init();
print_spew("In romstage.c:main()\r\n"); print_spew("In romstage.c:main()\n");
enable_smbus(); enable_smbus();
smbus_fixup(&ctrl); smbus_fixup(&ctrl);
if (bist == 0) { if (bist == 0) {
print_debug("doing early_mtrr\r\n"); print_debug("doing early_mtrr\n");
early_mtrr_init(); early_mtrr_init();
} }
/* Halt if there was a built-in self test failure. */ /* Halt if there was a built-in self test failure. */
report_bist_failure(bist); report_bist_failure(bist);
print_debug("Enabling mainboard devices\r\n"); print_debug("Enabling mainboard devices\n");
enable_mainboard_devices(); enable_mainboard_devices();
ddr_ram_setup(&ctrl); ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */ /* ram_check(0, 640 * 1024); */
print_spew("Leaving romstage.c:main()\r\n"); print_spew("Leaving romstage.c:main()\n");
} }

2
src/mainboard/kontron/kt690/romstage.c
View File

@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/lippert/frontrunner/romstage.c
View File

@ -24,7 +24,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
msr_t msr; msr_t msr;
/* 1. Initialize GLMC registers base on SPD values, /* 1. Initialize GLMC registers base on SPD values,
* Hard coded as XpressROM for now */ * Hard coded as XpressROM for now */
//print_debug("sdram_enable step 1\r\n"); //print_debug("sdram_enable step 1\n");
msr = rdmsr(0x20000018); msr = rdmsr(0x20000018);
msr.hi = 0x10076013; msr.hi = 0x10076013;
msr.lo = 0x3400; msr.lo = 0x3400;

4
src/mainboard/lippert/spacerunner-lx/romstage.c
View File

@ -91,7 +91,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
print_err("ERROR: spd_read_byte(DIMM0, 0x"); print_err("ERROR: spd_read_byte(DIMM0, 0x");
print_err_hex8(address); print_err_hex8(address);
print_err(") returns 0xff\r\n"); print_err(") returns 0xff\n");
} }
#endif #endif
@ -222,7 +222,7 @@ void cache_as_ram_main(void)
if ((err = smc_send_config(SMC_CONFIG))) { if ((err = smc_send_config(SMC_CONFIG))) {
print_err("ERROR "); print_err("ERROR ");
print_err_char('0'+err); print_err_char('0'+err);
print_err(" sending config data to SMC\r\n"); print_err(" sending config data to SMC\n");
} }
sdram_initialize(1, memctrl); sdram_initialize(1, memctrl);

2
src/mainboard/msi/ms7135/romstage.c
View File

@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/msi/ms7260/ap_romstage.c
View File

@ -72,7 +72,7 @@ void hardwaremain(int ret_addr)
*/ */
print_debug("CODE IN CACHE ON NODE:"); print_debug("CODE IN CACHE ON NODE:");
print_debug_hex8(id.nodeid); print_debug_hex8(id.nodeid);
print_debug("\r\n"); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);

8
src/mainboard/msi/ms7260/romstage.c
View File

@ -190,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid); print_debug_hex8(bsp_apicid);
print_debug("\r\n"); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */ /* In BSP so could hold all AP until sysinfo is in RAM. */
@ -220,7 +220,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("begin msr fid, vid "); print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo); print_debug_hex32(msr.lo);
print_debug("\r\n"); print_debug("\n");
} }
enable_fid_change(); enable_fid_change();
@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("end msr fid, vid "); print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo); print_debug_hex32(msr.lo);
print_debug("\r\n"); print_debug("\n");
} }
#endif #endif
@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */ /* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);

8
src/mainboard/msi/ms9185/romstage.c
View File

@ -204,7 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device(PCI_DEV(0, 0x19, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif #endif
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
setup_coherent_ht_domain(); setup_coherent_ht_domain();
@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }
#endif #endif

2
src/mainboard/msi/ms9282/romstage.c
View File

@ -214,7 +214,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= mcp55_early_setup_x(); needs_reset |= mcp55_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/newisys/khepri/romstage.c
View File

@ -168,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/nvidia/l1_2pvv/ap_romstage.c
View File

@ -82,7 +82,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x(); id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);

8
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -215,7 +215,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init(); console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -241,7 +241,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -266,7 +266,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);

2
src/mainboard/olpc/btest/romstage.c
View File

@ -90,7 +90,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
print_debug("computed msr.hi "); print_debug("computed msr.hi ");
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug("\r\n"); print_debug("\n");
/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
/* well, it may be close. It's about 200,000 ticks */ /* well, it may be close. It's about 200,000 ticks */

2
src/mainboard/olpc/rev_a/romstage.c
View File

@ -90,7 +90,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
print_debug("computed msr.hi "); print_debug("computed msr.hi ");
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug("\r\n"); print_debug("\n");
/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
/* well, it may be close. It's about 200,000 ticks */ /* well, it may be close. It's about 200,000 ticks */

2
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -98,7 +98,7 @@ static u8 spd_read_byte(u8 device, u8 address)
print_debug_hex8(address); print_debug_hex8(address);
print_debug(" returns "); print_debug(" returns ");
print_debug_hex8(spdbytes[address]); print_debug_hex8(spdbytes[address]);
print_debug("\r\n"); print_debug("\n");
return spdbytes[address]; return spdbytes[address];
} }

2
src/mainboard/sunw/ultra40/romstage.c
View File

@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/supermicro/h8dme/ap_romstage.c
View File

@ -86,7 +86,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x(); id = get_node_core_id_x();
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);

20
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -94,7 +94,7 @@ static void dump_smbus_registers(void)
{ {
u32 device; u32 device;
print_debug("\r\n"); print_debug("\n");
for (device = 1; device < 0x80; device++) { for (device = 1; device < 0x80; device++) {
int j; int j;
if (smbus_read_byte(device, 0) < 0) if (smbus_read_byte(device, 0) < 0)
@ -108,12 +108,12 @@ static void dump_smbus_registers(void)
break; break;
} }
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
printk(BIOS_DEBUG, "\r\n%02x: ", j); printk(BIOS_DEBUG, "\n%02x: ", j);
} }
byte = status & 0xff; byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte); printk(BIOS_DEBUG, "%02x ", byte);
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -137,13 +137,13 @@ static inline void change_i2c_mux(unsigned device)
smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f); smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f);
int ret; int ret;
print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
dump_smbus_registers(); dump_smbus_registers();
ret = smbus_send_byte(SMBUS_SWITCH1, device); ret = smbus_send_byte(SMBUS_SWITCH1, device);
print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
dump_smbus_registers(); dump_smbus_registers();
ret = smbus_send_byte_one(SMBUS_SWITCH2, device); ret = smbus_send_byte_one(SMBUS_SWITCH2, device);
print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
dump_smbus_registers(); dump_smbus_registers();
} }
*/ */
@ -273,7 +273,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid); print_debug_hex8(bsp_apicid);
print_debug("\r\n"); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -303,7 +303,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("begin msr fid, vid "); print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo); print_debug_hex32(msr.lo);
print_debug("\r\n"); print_debug("\n");
} }
@ -320,7 +320,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("end msr fid, vid "); print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo); print_debug_hex32(msr.lo);
print_debug("\r\n"); print_debug("\n");
} }
#endif #endif
@ -332,7 +332,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }
#endif #endif

2
src/mainboard/supermicro/h8dmr/ap_romstage.c
View File

@ -86,7 +86,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x(); id = get_node_core_id_x();
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);

8
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_mb_resource_map(); setup_mb_resource_map();
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -254,7 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }
#endif #endif

64
src/mainboard/supermicro/x6dai_g/debug.c
View File

@ -12,7 +12,7 @@ static void print_reg(unsigned char index)
print_debug_hex8(index); print_debug_hex8(index);
print_debug(": 0x"); print_debug(": 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
return; return;
} }
@ -49,52 +49,52 @@ static void siodump(void)
int i; int i;
unsigned char data; unsigned char data;
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
print_debug("\r\n*** XBUS REGISTERS ***\r\n"); print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03); setup_func(0x03);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02); setup_func(0x02);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
print_debug("\r\n*** GPIO REGISTERS ***\r\n"); print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** GPIO VALUES ***\r\n"); print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a); data = inb(0x68a);
print_debug("\r\nGPDO 4: 0x"); print_debug("\nGPDO 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
data = inb(0x68b); data = inb(0x68b);
print_debug("\r\nGPDI 4: 0x"); print_debug("\nGPDI 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
#if 0 #if 0
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a); setup_func(0x0a);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09); setup_func(0x09);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
print_debug("\r\n*** RTC REGISTERS ***\r\n"); print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10); setup_func(0x10);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
@ -104,7 +104,7 @@ static void siodump(void)
print_reg(0xfe); print_reg(0xfe);
print_reg(0xff); print_reg(0xff);
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14); setup_func(0x14);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
@ -135,7 +135,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev)
int i; int i;
unsigned long bar; unsigned long bar;
print_debug("BAR 14 Dump\r\n"); print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14); bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) { for(i = 0; i <= 0x300; i+=4) {
@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#endif #endif
if((i%4)==0) { if((i%4)==0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex16(i); print_debug_hex16(i);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug_hex32(read32(bar + i)); print_debug_hex32(read32(bar + i));
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
static void dump_pci_devices(void) static void dump_pci_devices(void)
@ -209,7 +209,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\r\n"); print_debug("\n");
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
device = ctrl->channel0[i]; device = ctrl->channel0[i];
@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -275,14 +275,14 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
unsigned char byte; unsigned char byte;
if ((i % 16) == 0) { if ((i % 16) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(i); print_debug_hex8(i);
print_debug(": "); print_debug(": ");
} }
@ -290,7 +290,7 @@ void dump_spd_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);
@ -308,7 +308,7 @@ void dump_ipmi_registers(void)
while(device <= 0x42) { while(device <= 0x42) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("ipmi "); print_debug("ipmi ");
print_debug_hex8(device); print_debug_hex8(device);
@ -318,7 +318,7 @@ void dump_ipmi_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);

2
src/mainboard/supermicro/x6dai_g/watchdog.c
View File

@ -37,6 +37,6 @@ static void disable_esb6300_watchdog(void)
static void disable_watchdogs(void) static void disable_watchdogs(void)
{ {
disable_esb6300_watchdog(); disable_esb6300_watchdog();
print_debug("Watchdogs disabled\r\n"); print_debug("Watchdogs disabled\n");
} }

64
src/mainboard/supermicro/x6dhe_g/debug.c
View File

@ -12,7 +12,7 @@ static void print_reg(unsigned char index)
print_debug_hex8(index); print_debug_hex8(index);
print_debug(": 0x"); print_debug(": 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
return; return;
} }
@ -49,52 +49,52 @@ static void siodump(void)
int i; int i;
unsigned char data; unsigned char data;
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
print_debug("\r\n*** XBUS REGISTERS ***\r\n"); print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03); setup_func(0x03);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02); setup_func(0x02);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
print_debug("\r\n*** GPIO REGISTERS ***\r\n"); print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** GPIO VALUES ***\r\n"); print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a); data = inb(0x68a);
print_debug("\r\nGPDO 4: 0x"); print_debug("\nGPDO 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
data = inb(0x68b); data = inb(0x68b);
print_debug("\r\nGPDI 4: 0x"); print_debug("\nGPDI 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
#if 0 #if 0
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a); setup_func(0x0a);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09); setup_func(0x09);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
print_debug("\r\n*** RTC REGISTERS ***\r\n"); print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10); setup_func(0x10);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
@ -104,7 +104,7 @@ static void siodump(void)
print_reg(0xfe); print_reg(0xfe);
print_reg(0xff); print_reg(0xff);
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14); setup_func(0x14);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
@ -135,7 +135,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev)
int i; int i;
unsigned long bar; unsigned long bar;
print_debug("BAR 14 Dump\r\n"); print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14); bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) { for(i = 0; i <= 0x300; i+=4) {
@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#endif #endif
if((i%4)==0) { if((i%4)==0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex16(i); print_debug_hex16(i);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug_hex32(read32(bar + i)); print_debug_hex32(read32(bar + i));
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
static void dump_pci_devices(void) static void dump_pci_devices(void)
@ -209,7 +209,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\r\n"); print_debug("\n");
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
device = ctrl->channel0[i]; device = ctrl->channel0[i];
@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -275,14 +275,14 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
unsigned char byte; unsigned char byte;
if ((i % 16) == 0) { if ((i % 16) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(i); print_debug_hex8(i);
print_debug(": "); print_debug(": ");
} }
@ -290,7 +290,7 @@ void dump_spd_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);
@ -308,7 +308,7 @@ void dump_ipmi_registers(void)
while(device <= 0x42) { while(device <= 0x42) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("ipmi "); print_debug("ipmi ");
print_debug_hex8(device); print_debug_hex8(device);
@ -318,7 +318,7 @@ void dump_ipmi_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);

2
src/mainboard/supermicro/x6dhe_g/watchdog.c
View File

@ -94,6 +94,6 @@ static void disable_watchdogs(void)
// disable_sio_watchdog(NSC_WD_DEV); // disable_sio_watchdog(NSC_WD_DEV);
disable_esb6300_watchdog(); disable_esb6300_watchdog();
// disable_jarell_frb3(); // disable_jarell_frb3();
print_debug("Watchdogs disabled\r\n"); print_debug("Watchdogs disabled\n");
} }

64
src/mainboard/supermicro/x6dhe_g2/debug.c
View File

@ -12,7 +12,7 @@ static void print_reg(unsigned char index)
print_debug_hex8(index); print_debug_hex8(index);
print_debug(": 0x"); print_debug(": 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
return; return;
} }
@ -49,52 +49,52 @@ static void siodump(void)
int i; int i;
unsigned char data; unsigned char data;
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
print_debug("\r\n*** XBUS REGISTERS ***\r\n"); print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03); setup_func(0x03);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02); setup_func(0x02);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
print_debug("\r\n*** GPIO REGISTERS ***\r\n"); print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** GPIO VALUES ***\r\n"); print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a); data = inb(0x68a);
print_debug("\r\nGPDO 4: 0x"); print_debug("\nGPDO 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
data = inb(0x68b); data = inb(0x68b);
print_debug("\r\nGPDI 4: 0x"); print_debug("\nGPDI 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
#if 0 #if 0
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a); setup_func(0x0a);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09); setup_func(0x09);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
print_debug("\r\n*** RTC REGISTERS ***\r\n"); print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10); setup_func(0x10);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
@ -104,7 +104,7 @@ static void siodump(void)
print_reg(0xfe); print_reg(0xfe);
print_reg(0xff); print_reg(0xff);
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14); setup_func(0x14);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
@ -135,7 +135,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev)
int i; int i;
unsigned long bar; unsigned long bar;
print_debug("BAR 14 Dump\r\n"); print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14); bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) { for(i = 0; i <= 0x300; i+=4) {
@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#endif #endif
if((i%4)==0) { if((i%4)==0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex16(i); print_debug_hex16(i);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug_hex32(read32(bar + i)); print_debug_hex32(read32(bar + i));
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
static void dump_pci_devices(void) static void dump_pci_devices(void)
@ -209,7 +209,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\r\n"); print_debug("\n");
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
device = ctrl->channel0[i]; device = ctrl->channel0[i];
@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -275,14 +275,14 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
unsigned char byte; unsigned char byte;
if ((i % 16) == 0) { if ((i % 16) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(i); print_debug_hex8(i);
print_debug(": "); print_debug(": ");
} }
@ -290,7 +290,7 @@ void dump_spd_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);
@ -308,7 +308,7 @@ void dump_ipmi_registers(void)
while(device <= 0x42) { while(device <= 0x42) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("ipmi "); print_debug("ipmi ");
print_debug_hex8(device); print_debug_hex8(device);
@ -318,7 +318,7 @@ void dump_ipmi_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);

2
src/mainboard/supermicro/x6dhe_g2/watchdog.c
View File

@ -94,6 +94,6 @@ static void disable_watchdogs(void)
// disable_sio_watchdog(NSC_WD_DEV); // disable_sio_watchdog(NSC_WD_DEV);
disable_esb6300_watchdog(); disable_esb6300_watchdog();
// disable_jarell_frb3(); // disable_jarell_frb3();
print_debug("Watchdogs disabled\r\n"); print_debug("Watchdogs disabled\n");
} }

64
src/mainboard/supermicro/x6dhr_ig/debug.c
View File

@ -12,7 +12,7 @@ static void print_reg(unsigned char index)
print_debug_hex8(index); print_debug_hex8(index);
print_debug(": 0x"); print_debug(": 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
return; return;
} }
@ -49,52 +49,52 @@ static void siodump(void)
int i; int i;
unsigned char data; unsigned char data;
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
print_debug("\r\n*** XBUS REGISTERS ***\r\n"); print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03); setup_func(0x03);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02); setup_func(0x02);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
print_debug("\r\n*** GPIO REGISTERS ***\r\n"); print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** GPIO VALUES ***\r\n"); print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a); data = inb(0x68a);
print_debug("\r\nGPDO 4: 0x"); print_debug("\nGPDO 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
data = inb(0x68b); data = inb(0x68b);
print_debug("\r\nGPDI 4: 0x"); print_debug("\nGPDI 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
#if 0 #if 0
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a); setup_func(0x0a);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09); setup_func(0x09);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
print_debug("\r\n*** RTC REGISTERS ***\r\n"); print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10); setup_func(0x10);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
@ -104,7 +104,7 @@ static void siodump(void)
print_reg(0xfe); print_reg(0xfe);
print_reg(0xff); print_reg(0xff);
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14); setup_func(0x14);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
@ -135,7 +135,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev)
int i; int i;
unsigned long bar; unsigned long bar;
print_debug("BAR 14 Dump\r\n"); print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14); bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) { for(i = 0; i <= 0x300; i+=4) {
@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#endif #endif
if((i%4)==0) { if((i%4)==0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex16(i); print_debug_hex16(i);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug_hex32(read32(bar + i)); print_debug_hex32(read32(bar + i));
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
static void dump_pci_devices(void) static void dump_pci_devices(void)
@ -209,7 +209,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\r\n"); print_debug("\n");
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
device = ctrl->channel0[i]; device = ctrl->channel0[i];
@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -275,14 +275,14 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
unsigned char byte; unsigned char byte;
if ((i % 16) == 0) { if ((i % 16) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(i); print_debug_hex8(i);
print_debug(": "); print_debug(": ");
} }
@ -290,7 +290,7 @@ void dump_spd_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);
@ -308,7 +308,7 @@ void dump_ipmi_registers(void)
while(device <= 0x42) { while(device <= 0x42) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("ipmi "); print_debug("ipmi ");
print_debug_hex8(device); print_debug_hex8(device);
@ -318,7 +318,7 @@ void dump_ipmi_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);

2
src/mainboard/supermicro/x6dhr_ig/watchdog.c
View File

@ -94,6 +94,6 @@ static void disable_watchdogs(void)
// disable_sio_watchdog(NSC_WD_DEV); // disable_sio_watchdog(NSC_WD_DEV);
disable_ich5_watchdog(); disable_ich5_watchdog();
// disable_jarell_frb3(); // disable_jarell_frb3();
print_debug("Watchdogs disabled\r\n"); print_debug("Watchdogs disabled\n");
} }

64
src/mainboard/supermicro/x6dhr_ig2/debug.c
View File

@ -12,7 +12,7 @@ static void print_reg(unsigned char index)
print_debug_hex8(index); print_debug_hex8(index);
print_debug(": 0x"); print_debug(": 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
return; return;
} }
@ -49,52 +49,52 @@ static void siodump(void)
int i; int i;
unsigned char data; unsigned char data;
print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); print_debug("\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
print_debug("\r\n*** XBUS REGISTERS ***\r\n"); print_debug("\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03); setup_func(0x03);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02); setup_func(0x02);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
print_debug("\r\n*** GPIO REGISTERS ***\r\n"); print_debug("\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
print_debug("\r\n*** GPIO VALUES ***\r\n"); print_debug("\n*** GPIO VALUES ***\n");
data = inb(0x68a); data = inb(0x68a);
print_debug("\r\nGPDO 4: 0x"); print_debug("\nGPDO 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
data = inb(0x68b); data = inb(0x68b);
print_debug("\r\nGPDI 4: 0x"); print_debug("\nGPDI 4: 0x");
print_debug_hex8(data); print_debug_hex8(data);
print_debug("\r\n"); print_debug("\n");
#if 0 #if 0
print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a); setup_func(0x0a);
print_reg(0xf0); print_reg(0xf0);
print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); print_debug("\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09); setup_func(0x09);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
print_debug("\r\n*** RTC REGISTERS ***\r\n"); print_debug("\n*** RTC REGISTERS ***\n");
setup_func(0x10); setup_func(0x10);
print_reg(0xf0); print_reg(0xf0);
print_reg(0xf1); print_reg(0xf1);
@ -104,7 +104,7 @@ static void siodump(void)
print_reg(0xfe); print_reg(0xfe);
print_reg(0xff); print_reg(0xff);
print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14); setup_func(0x14);
print_reg(0xf0); print_reg(0xf0);
#endif #endif
@ -135,7 +135,7 @@ static void print_pci_devices(void)
continue; continue;
} }
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
} }
} }
@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
print_debug_pci_dev(dev); print_debug_pci_dev(dev);
print_debug("\r\n"); print_debug("\n");
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' '); print_debug_char(' ');
print_debug_hex8(val); print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev)
int i; int i;
unsigned long bar; unsigned long bar;
print_debug("BAR 14 Dump\r\n"); print_debug("BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14); bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) { for(i = 0; i <= 0x300; i+=4) {
@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
#endif #endif
if((i%4)==0) { if((i%4)==0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex16(i); print_debug_hex16(i);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug_hex32(read32(bar + i)); print_debug_hex32(read32(bar + i));
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
static void dump_pci_devices(void) static void dump_pci_devices(void)
@ -209,7 +209,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_spd_registers(const struct mem_controller *ctrl)
{ {
int i; int i;
print_debug("\r\n"); print_debug("\n");
for(i = 0; i < 4; i++) { for(i = 0; i < 4; i++) {
unsigned device; unsigned device;
device = ctrl->channel0[i]; device = ctrl->channel0[i];
@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
device = ctrl->channel1[i]; device = ctrl->channel1[i];
if (device) { if (device) {
@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status; int status;
unsigned char byte; unsigned char byte;
if ((j & 0xf) == 0) { if ((j & 0xf) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(j); print_debug_hex8(j);
print_debug(": "); print_debug(": ");
} }
status = smbus_read_byte(device, j); status = smbus_read_byte(device, j);
if (status < 0) { if (status < 0) {
print_debug("bad device\r\n"); print_debug("bad device\n");
break; break;
} }
byte = status & 0xff; byte = status & 0xff;
print_debug_hex8(byte); print_debug_hex8(byte);
print_debug_char(' '); print_debug_char(' ');
} }
print_debug("\r\n"); print_debug("\n");
} }
} }
} }
@ -275,14 +275,14 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("dimm "); print_debug("dimm ");
print_debug_hex8(device); print_debug_hex8(device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
unsigned char byte; unsigned char byte;
if ((i % 16) == 0) { if ((i % 16) == 0) {
print_debug("\r\n"); print_debug("\n");
print_debug_hex8(i); print_debug_hex8(i);
print_debug(": "); print_debug(": ");
} }
@ -290,7 +290,7 @@ void dump_spd_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);
@ -308,7 +308,7 @@ void dump_ipmi_registers(void)
while(device <= 0x42) { while(device <= 0x42) {
int status = 0; int status = 0;
int i; int i;
print_debug("\r\n"); print_debug("\n");
print_debug("ipmi "); print_debug("ipmi ");
print_debug_hex8(device); print_debug_hex8(device);
@ -318,7 +318,7 @@ void dump_ipmi_registers(void)
if (status < 0) { if (status < 0) {
print_debug("bad device: "); print_debug("bad device: ");
print_debug_hex8(-status); print_debug_hex8(-status);
print_debug("\r\n"); print_debug("\n");
break; break;
} }
print_debug_hex8(status); print_debug_hex8(status);

2
src/mainboard/supermicro/x6dhr_ig2/watchdog.c
View File

@ -94,6 +94,6 @@ static void disable_watchdogs(void)
// disable_sio_watchdog(NSC_WD_DEV); // disable_sio_watchdog(NSC_WD_DEV);
disable_ich5_watchdog(); disable_ich5_watchdog();
// disable_jarell_frb3(); // disable_jarell_frb3();
print_debug("Watchdogs disabled\r\n"); print_debug("Watchdogs disabled\n");
} }

2
src/mainboard/technexion/tim5690/romstage.c
View File

@ -184,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/technexion/tim8690/romstage.c
View File

@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

48
src/mainboard/technologic/ts5300/romstage.c
View File

@ -56,18 +56,18 @@ static void identify_ts9500(void)
TS9500_LED_ON; TS9500_LED_ON;
print_err("TS-9500 add-on found:\r\n"); print_err("TS-9500 add-on found:\n");
val=inb(0x19b); val=inb(0x19b);
for (i=0; i<8; i++) { for (i=0; i<8; i++) {
print_err(" DIP"); print_err(" DIP");
print_err_char(i+0x31); print_err_char(i+0x31);
print_err(": "); print_err(": ");
if((val&(1<<i))!=0) if((val&(1<<i))!=0)
print_err("on\r\n"); print_err("on\n");
else else
print_err("off\r\n"); print_err("off\n");
} }
print_err("\r\n"); print_err("\n");
val=inb(0x19a); val=inb(0x19a);
@ -76,11 +76,11 @@ static void identify_ts9500(void)
print_err_char(i+0x30-5); print_err_char(i+0x30-5);
print_err(": "); print_err(": ");
if((val&(1<<i))!=0) if((val&(1<<i))!=0)
print_err("on\r\n"); print_err("on\n");
else else
print_err("off\r\n"); print_err("off\n");
} }
print_err("\r\n"); print_err("\n");
TS9500_LED_OFF; TS9500_LED_OFF;
} }
@ -92,29 +92,29 @@ static void identify_system(void)
print_err("Mainboard: "); print_err("Mainboard: ");
val=inb(0x74); val=inb(0x74);
switch(val) { switch(val) {
case 0x50: print_err("TS-5300\r\n"); break; case 0x50: print_err("TS-5300\n"); break;
case 0x40: print_err("TS-5400\r\n"); break; case 0x40: print_err("TS-5400\n"); break;
case 0x60: print_err("TS-5500\r\n"); break; case 0x60: print_err("TS-5500\n"); break;
case 0x20: print_err("TS-5600\r\n"); break; case 0x20: print_err("TS-5600\n"); break;
case 0x70: print_err("TS-5700\r\n"); break; case 0x70: print_err("TS-5700\n"); break;
default: print_err("unknown\r\n"); break; default: print_err("unknown\n"); break;
} }
val=inb(0x75); val=inb(0x75);
print_err(" SRAM option: "); print_err(" SRAM option: ");
if((val&1)==0) print_err("not "); if((val&1)==0) print_err("not ");
print_err("installed\r\n"); print_err("installed\n");
print_err(" RS-485 option: "); print_err(" RS-485 option: ");
if((val&2)==0) print_err("not "); if((val&2)==0) print_err("not ");
print_err("installed\r\n"); print_err("installed\n");
val=inb(0x76); val=inb(0x76);
print_err(" Temp. range: "); print_err(" Temp. range: ");
if((val&2)==0) print_err("commercial\r\n"); if((val&2)==0) print_err("commercial\n");
else print_err("industrial\r\n"); else print_err("industrial\n");
print_err("\r\n"); print_err("\n");
val=inb(0x77); val=inb(0x77);
for (i=1; i<8; i++) { for (i=1; i<8; i++) {
@ -122,11 +122,11 @@ static void identify_system(void)
print_err_char(i+0x30); print_err_char(i+0x30);
print_err(": "); print_err(": ");
if((val&(1<<i))!=0) if((val&(1<<i))!=0)
print_err("on\r\n"); print_err("on\n");
else else
print_err("off\r\n"); print_err("off\n");
} }
print_err("\r\n"); print_err("\n");
/* Detect TS-9500 */ /* Detect TS-9500 */
val=inb(0x19d); val=inb(0x19d);
@ -157,9 +157,9 @@ static void main(unsigned long bist)
console_init(); console_init();
print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\r\n"); print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n");
staticmem(); staticmem();
print_err("Memory initialized: 32MB\r\n"); print_err("Memory initialized: 32MB\n");
#if 1 #if 1
identify_system(); identify_system();
@ -167,7 +167,7 @@ static void main(unsigned long bist)
#if 0 #if 0
// Check 32MB of memory @ 0 (very slow!) // Check 32MB of memory @ 0 (very slow!)
print_err("Checking memory:\r\n"); print_err("Checking memory:\n");
ram_check(0x00000000, 0x000a0000); ram_check(0x00000000, 0x000a0000);
ram_check(0x000b0000, 0x02000000); ram_check(0x000b0000, 0x02000000);
#endif #endif

20
src/mainboard/tyan/s2735/romstage.c
View File

@ -129,9 +129,9 @@ void amd64_main(unsigned long bist)
: "=a" (v_esp) : "=a" (v_esp)
); );
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
#else #else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\n");
#endif #endif
} }
@ -141,9 +141,9 @@ void amd64_main(unsigned long bist)
cpu_reset_x: cpu_reset_x:
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset); printk(BIOS_DEBUG, "cpu_reset = %08x\n",cpu_reset);
#else #else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\n");
#endif #endif
if(cpu_reset == 0) { if(cpu_reset == 0) {
@ -184,21 +184,21 @@ cpu_reset_x:
/* We can not go back any more, we lost old stack data in cache as ram*/ /* We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) { if(new_cpu_reset==0) {
print_debug("Use Ram as Stack now - done\r\n"); print_debug("Use Ram as Stack now - done\n");
} else } else
{ {
print_debug("Use Ram as Stack now - \r\n"); print_debug("Use Ram as Stack now - \n");
} }
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
#else #else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\n");
#endif #endif
#ifdef DEACTIVATE_CAR #ifdef DEACTIVATE_CAR
print_debug("Deactivating CAR"); print_debug("Deactivating CAR");
#include DEACTIVATE_CAR_FILE #include DEACTIVATE_CAR_FILE
print_debug(" - Done.\r\n"); print_debug(" - Done.\n");
#endif #endif
/*copy and execute coreboot_ram */ /*copy and execute coreboot_ram */
copy_and_run(new_cpu_reset); copy_and_run(new_cpu_reset);
@ -206,7 +206,7 @@ cpu_reset_x:
} }
#endif #endif
print_debug("should not be here -\r\n"); print_debug("should not be here -\n");
} }

2
src/mainboard/tyan/s2850/romstage.c
View File

@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2875/romstage.c
View File

@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2880/romstage.c
View File

@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2881/romstage.c
View File

@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2882/romstage.c
View File

@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2885/romstage.c
View File

@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2891/romstage.c
View File

@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
printk(BIOS_INFO, "ht reset -\r\n"); printk(BIOS_INFO, "ht reset -\n");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2912/ap_romstage.c
View File

@ -79,7 +79,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x(); id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);

8
src/mainboard/tyan/s2912/romstage.c
View File

@ -211,7 +211,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init(); console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@ -237,7 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
@ -251,7 +251,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
} }
#endif #endif
@ -262,7 +262,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

8
src/mainboard/tyan/s4880/romstage.c
View File

@ -66,11 +66,11 @@ static inline void change_i2c_mux(unsigned device)
{ {
#define SMBUS_HUB 0x18 #define SMBUS_HUB 0x18
int ret; int ret;
print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
ret = smbus_write_byte(SMBUS_HUB, 0x01, device); ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
} }
#endif #endif
@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

8
src/mainboard/tyan/s4882/romstage.c
View File

@ -70,14 +70,14 @@ static inline void change_i2c_mux(unsigned device)
{ {
#define SMBUS_HUB 0x18 #define SMBUS_HUB 0x18
int ret, i; int ret, i;
print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
i=2; i=2;
do { do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device); ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
} while ((ret!=0) && (i-->0)); } while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
} }
#endif #endif
@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\n");
soft_reset(); soft_reset();
} }

8
src/mainboard/via/epia-cn/romstage.c
View File

@ -98,26 +98,26 @@ static void main(unsigned long bist)
uart_init(); uart_init();
console_init(); console_init();
print_spew("In romstage.c:main()\r\n"); print_spew("In romstage.c:main()\n");
enable_smbus(); enable_smbus();
smbus_fixup(&ctrl); smbus_fixup(&ctrl);
if (bist == 0) { if (bist == 0) {
print_debug("doing early_mtrr\r\n"); print_debug("doing early_mtrr\n");
early_mtrr_init(); early_mtrr_init();
} }
/* Halt if there was a built-in self test failure. */ /* Halt if there was a built-in self test failure. */
report_bist_failure(bist); report_bist_failure(bist);
print_debug("Enabling mainboard devices\r\n"); print_debug("Enabling mainboard devices\n");
enable_mainboard_devices(); enable_mainboard_devices();
ddr_ram_setup(&ctrl); ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */ /* ram_check(0, 640 * 1024); */
print_spew("Leaving romstage.c:main()\r\n"); print_spew("Leaving romstage.c:main()\n");
} }

10
src/mainboard/via/epia-m/romstage.c
View File

@ -102,7 +102,7 @@ static void main(unsigned long bist)
enable_smbus(); enable_smbus();
print_spew("In romstage.c:main()\r\n"); print_spew("In romstage.c:main()\n");
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
@ -111,10 +111,10 @@ static void main(unsigned long bist)
outb(5, 0x80); outb(5, 0x80);
print_debug(" Enabling mainboard devices\r\n"); print_debug(" Enabling mainboard devices\n");
enable_mainboard_devices(); enable_mainboard_devices();
print_debug(" Enabling shadow ram\r\n"); print_debug(" Enabling shadow ram\n");
enable_shadow_ram(); enable_shadow_ram();
ddr_ram_setup((const struct mem_controller *)0); ddr_ram_setup((const struct mem_controller *)0);
@ -141,12 +141,12 @@ static void main(unsigned long bist)
#endif #endif
if (bist == 0) { if (bist == 0) {
print_debug(" Doing MTRR init.\r\n"); print_debug(" Doing MTRR init.\n");
early_mtrr_init(); early_mtrr_init();
} }
//dump_pci_devices(); //dump_pci_devices();
print_spew("Leaving romstage.c:main()\r\n"); print_spew("Leaving romstage.c:main()\n");
} }

38
src/mainboard/via/epia-m700/romstage.c
View File

@ -76,13 +76,13 @@ int acpi_is_wakeup_early_via_vx800(void)
device_t dev; device_t dev;
u16 tmp, result; u16 tmp, result;
print_debug("In acpi_is_wakeup_early_via_vx800\r\n"); print_debug("In acpi_is_wakeup_early_via_vx800\n");
/* Power management controller */ /* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX855_LPC), 0); PCI_DEVICE_ID_VIA_VX855_LPC), 0);
if (dev == PCI_DEV_INVALID) if (dev == PCI_DEV_INVALID)
die("Power management controller not found\r\n"); die("Power management controller not found\n");
/* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
@ -94,7 +94,7 @@ int acpi_is_wakeup_early_via_vx800(void)
result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
print_debug(" boot_mode="); print_debug(" boot_mode=");
print_debug_hex16(result); print_debug_hex16(result);
print_debug("\r\n"); print_debug("\n");
return result; return result;
} }
@ -142,7 +142,7 @@ static void enable_mainboard_devices(void)
pci_write_config8(dev, 0x5b, 0x01); pci_write_config8(dev, 0x5b, 0x01);
#endif #endif
print_debug("In enable_mainboard_devices \r\n"); print_debug("In enable_mainboard_devices \n");
/* Enable P2P Bridge Header for external PCI bus. */ /* Enable P2P Bridge Header for external PCI bus. */
dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
@ -482,7 +482,7 @@ void amd64_main(unsigned long bist)
* early_mtrr_init() call. * early_mtrr_init() call.
*/ */
#if 0 #if 0
print_debug("doing early_mtrr\r\n"); print_debug("doing early_mtrr\n");
early_mtrr_init(); early_mtrr_init();
#endif #endif
} }
@ -490,7 +490,7 @@ void amd64_main(unsigned long bist)
/* Halt if there was a built-in self test failure. */ /* Halt if there was a built-in self test failure. */
report_bist_failure(bist); report_bist_failure(bist);
print_debug("Enabling mainboard devices\r\n"); print_debug("Enabling mainboard devices\n");
enable_mainboard_devices(); enable_mainboard_devices();
/* /*
@ -501,7 +501,7 @@ void amd64_main(unsigned long bist)
Data = pci_read_config8(device, 0xf6); Data = pci_read_config8(device, 0xf6);
print_debug("NB chip revision ="); print_debug("NB chip revision =");
print_debug_hex8(Data); print_debug_hex8(Data);
print_debug("\r\n"); print_debug("\n");
/* Make NB ready before DRAM init. */ /* Make NB ready before DRAM init. */
via_pci_inittable(Data, mNbStage1InitTbl); via_pci_inittable(Data, mNbStage1InitTbl);
@ -518,7 +518,7 @@ void amd64_main(unsigned long bist)
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
DRAM_SYS_ATTR DramAttr; DRAM_SYS_ATTR DramAttr;
print_debug("This is an S3 wakeup\r\n"); print_debug("This is an S3 wakeup\n");
memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
/* /*
@ -553,7 +553,7 @@ void amd64_main(unsigned long bist)
/* Just copy this function from draminit to here! */ /* Just copy this function from draminit to here! */
SetUMARam(); SetUMARam();
print_debug("Resume from S3, RAM init was ignored\r\n"); print_debug("Resume from S3, RAM init was ignored\n");
} else { } else {
ddr2_ram_setup(); ddr2_ram_setup();
ram_check(0, 640 * 1024); ram_check(0, 640 * 1024);
@ -675,7 +675,7 @@ void amd64_main(unsigned long bist)
); );
#endif #endif
/* This can have function call, because no variable used before this. */ /* This can have function call, because no variable used before this. */
print_debug("Copy memory to high memory to protect s3 wakeup vector code \r\n"); print_debug("Copy memory to high memory to protect s3 wakeup vector code \n");
memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
0x100000), (unsigned char *)0, 0xa0000); 0x100000), (unsigned char *)0, 0xa0000);
memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
@ -725,11 +725,11 @@ void amd64_main(unsigned long bist)
unsigned v_esp; unsigned v_esp;
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)); __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp));
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
#else #else
print_debug("v_esp="); print_debug("v_esp=");
print_debug_hex32(v_esp); print_debug_hex32(v_esp);
print_debug("\r\n"); print_debug("\n");
#endif #endif
} }
#endif #endif
@ -744,11 +744,11 @@ cpu_reset_x:
cpu_reset = 0; cpu_reset = 0;
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
#else #else
print_debug("cpu_reset = "); print_debug("cpu_reset = ");
print_debug_hex32(cpu_reset); print_debug_hex32(cpu_reset);
print_debug("\r\n"); print_debug("\n");
#endif #endif
if (cpu_reset == 0) if (cpu_reset == 0)
@ -789,16 +789,16 @@ cpu_reset_x:
/* We can't go back anymore, we lost old stack data in CAR. */ /* We can't go back anymore, we lost old stack data in CAR. */
if (new_cpu_reset == 0) if (new_cpu_reset == 0)
print_debug("Use Ram as Stack now - done\r\n"); print_debug("Use Ram as Stack now - done\n");
else else
print_debug("Use Ram as Stack now - \r\n"); print_debug("Use Ram as Stack now - \n");
#if CONFIG_USE_PRINTK_IN_CAR #if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
#else #else
print_debug("new_cpu_reset = "); print_debug("new_cpu_reset = ");
print_debug_hex32(new_cpu_reset); print_debug_hex32(new_cpu_reset);
print_debug("\r\n"); print_debug("\n");
#endif #endif
jason_tsc_count_car(); jason_tsc_count_car();
@ -808,6 +808,6 @@ cpu_reset_x:
} }
#endif #endif
print_debug("should not be here -\r\n"); print_debug("should not be here -\n");
} }

12
src/mainboard/via/epia-n/romstage.c
View File

@ -124,7 +124,7 @@ static void main(unsigned long bist)
uart_init(); uart_init();
console_init(); console_init();
print_spew("In romstage.c:main()\r\n"); print_spew("In romstage.c:main()\n");
enable_smbus(); enable_smbus();
smbus_fixup(&ctrl); smbus_fixup(&ctrl);
@ -132,25 +132,25 @@ static void main(unsigned long bist)
/* Halt if there was a built-in self test failure. */ /* Halt if there was a built-in self test failure. */
report_bist_failure(bist); report_bist_failure(bist);
print_debug("Enabling mainboard devices\r\n"); print_debug("Enabling mainboard devices\n");
enable_mainboard_devices(); enable_mainboard_devices();
print_debug("Enable F-ROM Shadow RAM\r\n"); print_debug("Enable F-ROM Shadow RAM\n");
enable_shadow_ram(); enable_shadow_ram();
/* setup cpu */ /* setup cpu */
print_debug("Setup CPU Interface\r\n"); print_debug("Setup CPU Interface\n");
c3_cpu_setup(ctrl.d0f2); c3_cpu_setup(ctrl.d0f2);
ddr_ram_setup(); ddr_ram_setup();
if (bist == 0) { if (bist == 0) {
print_debug("doing early_mtrr\r\n"); print_debug("doing early_mtrr\n");
early_mtrr_init(); early_mtrr_init();
} }
//ram_check(0, 640 * 1024); //ram_check(0, 640 * 1024);
print_spew("Leaving romstage.c:main()\r\n"); print_spew("Leaving romstage.c:main()\n");
} }

Some files were not shown because too many files have changed in this diff Show More