drivers/intel/fsp2_0: Hook up IntelFSP repo

With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using
Intel's FSP repo (that we mirror) to build a complete BIOS ifd region
with a simple coreboot build, automatically drawing in headers and
binaries.

This commit covers Apollolake, Coffeelake, Skylake, and Kabylake.

Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's
also supports Skylake.

Another candidate (given 3rdparty/fsp's content) is Denverton NS, but
it requires changes to coreboot's FSP bindings to become compatible.

Cannonlake, Whiskeylake require an FSP release.

Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28593
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/apollolake/Kconfig

@@ -202,6 +202,16 @@ config VERSTAGE_ADDR
 	help
 	  The base address (in CAR) where verstage should be linked
 
+config FSP_HEADER_PATH
+	string
+	default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GLK
+	default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/"
+
+config FSP_FD_PATH
+	string
+	depends on FSP_USE_REPO
+	default "3rdparty/fsp/ApolloLakeFspBinPkg/FspBin/Fsp.fd"
+
 config FSP_M_ADDR
 	hex
 	default 0xfef40000

src/soc/intel/apollolake/Makefile.inc

@@ -100,11 +100,6 @@ ramstage-y += gpio_apl.c
 endif
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
-ifeq ($(CONFIG_SOC_INTEL_GLK),y)
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk
-else
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake
-endif
 
 # Since FSP-M runs in CAR we need to relocate it to a specific address
 $(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)