From 654a08acd43c6bd588784d142f16a19d80736183 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 10 Feb 2023 13:43:56 -0700 Subject: [PATCH] oryp11: dGPU port and TP GPIO Change-Id: Ie3f9edbf5cb9fcaba3c50e949afb55f990cd846d Signed-off-by: Tim Crawford --- src/mainboard/system76/rpl/variants/oryp11/gpio.c | 2 +- src/mainboard/system76/rpl/variants/oryp11/overridetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/system76/rpl/variants/oryp11/gpio.c b/src/mainboard/system76/rpl/variants/oryp11/gpio.c index d0d9c7e5e2..94f2d6aa47 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/gpio.c +++ b/src/mainboard/system76/rpl/variants/oryp11/gpio.c @@ -122,7 +122,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E4, NONE), PAD_NC(GPP_E5, NONE), PAD_NC(GPP_E6, NONE), - _PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000), // TP_ATTN# + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN# PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# diff --git a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb index 5e9d0d159e..9236e9a710 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb @@ -18,7 +18,7 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # AJ_USB2 (USB 3.2 Gen2 + charger) end - device ref pcie5_1 off + device ref pcie5_0 on # CPU PCIe RP#2 x8, Clock 14 (DGPU) register "cpu_pcie_rp[CPU_RP(2)]" = "{ .clk_src = 14,