{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate

Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/cpu/intel/car/romstage.c

@@ -74,7 +74,7 @@ void *setup_stack_and_mtrrs(void)
 	postcar_frame_init_lowmem(&pcf);
 
 	/* Cache the ROM as WP just below 4GiB. */
-	postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
 		MTRR_TYPE_WRPROT);
 
 	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */

src/cpu/intel/fsp_model_406dx/bootblock.c

@@ -62,8 +62,7 @@ static void enable_rom_caching(void)
 	msr_t msr;
 
 	disable_cache();
-	set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1,
-		     CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
 	enable_cache();
 
 	/* Enable Variable MTRRs */