sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate

Browse Source 
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Nico Huber
2018-05-27 13:52:28 +02:00
parent 6197b76988
commit 654cc2fe10
10 changed files with 10 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/x4x/ram_calc.c
View File

@@ -116,7 +116,7 @@ void *setup_stack_and_mtrrs(void)
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */