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soc/intel/quark: Enable HSUART1

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Enable HSUART1 for debug serial output.  Specify the fixed resources in
the UART driver.  This keeps debug serial output flowing during the rest
of the device initialization.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing successful if:
   *  Debug serial output stays enabled after BS_DEV_RESOURCES state

Change-Id: Ica02e5fece156b21d4a3889284ca467d55c7880d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13730
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
2016-02-17 08:47:58 -08:00
committed by Leroy P Leahy
parent 535333dd54
commit 654fd0703a
4 changed files with 59 additions and 17 deletions
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3
src/soc/intel/quark/Makefile.inc
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@@ -20,12 +20,13 @@ subdirs-y += ../../../cpu/x86/tsc
romstage-y += memmap.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-y += chip.c
ramstage-y += memmap.c
ramstage-y += northcluster.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark